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WED416S16030A Datasheet(PDF) 4 Page - White Electronic Designs Corporation

Part # WED416S16030A
Description  4M x 16 Bits x 4 Banks Synchronous DRAM
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Manufacturer  WEDC [White Electronic Designs Corporation]
Direct Link  http://www.whiteedc.com
Logo WEDC - White Electronic Designs Corporation

WED416S16030A Datasheet(HTML) 4 Page - White Electronic Designs Corporation

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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED416S16030A
April 2006
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
OPERATING AC PARAMETERS
(Vcc = 3.3V, -40°C ≤ Ta ≤ +85°C)
Parameter
Symbol
7
75
8
10
Unit
Notes
Clock Cycle Time
CAS latency = 3
tCK
7.5
7.5
8
10
ns
1
CAS latency = 2
7.5
8
10
1
Clock to Valid Output Delay
tAC
5.4
6
6
7
ns
1,2
Output Data Hold Time
tOH
3
3
3
3
ns
2
Clock High Pulse Width
tCH
2.5
2.5
3
3
ns
3
Clock Low Pulse Width
tCL
2.5
2.5
3
3
ns
3
Input Setup Time
tCMS
1.5
1.5
2
2
ns
3
Input Hold Time
tCMH
0.8
0.8
1
1
ns
3
Clock to Output in Low-Z
tLZ
1
1
1
1
ns
2
Clock to Output in High-Z
tHZ
5.4
6
6
7
ns
Row Active to Row Active Delay
tRRD
15
15
20
20
ns
4
RAS# to CAS# Delay
tRCD
20
20
20
20
ns
4
Row Precharge Time
tRP
20
20
20
20
ns
4
Row Active Time
tRAS
45
45
50
50
ns
4
Row Cycle Time - Operation
tRC
65
65
70
70
ns
4
Last Data In to New Column Address Delay
tCDL
1
1
1
1
CK
5
Last Data In to Row Precharge
tRDL
2
2
2
2
CK
5
Last Data In to Burst Stop
tBDL
1
1
1
1
CK
5
Column Address to Column Address Delay
tCCD
1
1
1
1
CK
6
Number of Valid Output Data
CAS latency = 3
2
2
2
2
ea
7
CAS latency = 2
1
1
1
1
Data Setup Time
tDS
1.5
1.5
2
2
ns
Data Hold Time
tDH
0.8
0.8
1
1
ns
NOTES:
1.
Parameters depend on programmed CAS latency.
2.
If clock rise time is longer than 1ns, (tRISE 2-0.5)ns should be added to the parameter.
3.
Assumed input rise and fall time = 1ns. If tRISE & tFALL are longer than 1ns, [(tRISE + tFALL)/2]-1ns should be added to the parameter.
4.
The minimum number of clock cycles required is determined by dividing the minimum time required by the clock cycle time and then
rounding up to the next higher integer.
5.
Minimum delay is required to complete write.
6.
All devices allow every cycle column address changes.
7.
In case of row precharge interrupt, auto precharge and read burst stop.
AC CHARACTERISTICS


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