White Electronic Designs

February 2005

Rev. 3

WEDPN16M72V-XB2X

6

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

FIGURE 4 – CAS LATENCY

or incompatibility with future versions may result.

OPERATING MODE

The normal operating mode is selected by setting M7and

M8 to zero; the other combinations of values for M7 and

M8 are reserved for future use and/or test modes. The

programmed burst length applies to both READ and

WRITE bursts.

Test modes and reserved states should not be used

because unknown operation or incompatibility with future

versions may result.

TABLE 2 - CAS LATENCY

SPEED

ALLOWABLE OPERATING

FREQUENCY (MHz)

CAS LATENCY = 2

CAS LATENCY = 3

-100

≤75

≤100

-125

≤100

≤125

-133

≤100

≤133

WRITE BURST MODE

When M9 = 0, the burst length programmed via M0-M2

applies to both READ and WRITE bursts; when M9 = 1,

the programmed burst length applies to READ bursts, but

write accesses are single-location (nonburst) accesses.

CLK

I/O

T2

T1

T3

T0

CAS Latency = 3

LZ

t

COMMAND

NOP

READ

NOP

T4

NOP

DON’T CARE

UNDEFINED

CLK

I/O

T2

T1

T3

T0

CAS Latency = 2

LZ

t

COMMAND

NOP

READ

NOP

BURST TYPE

Accesses within a given burst may be programmed to be

either sequential or interleaved; this is referred to as the

burst type and is selected via bit M3.

The ordering of accesses within a burst is determined by

the burst length, the burst type and the starting column

address, as shown in Table 1.

CAS LATENCY

The CAS latency is the delay, in clock cycles, between

the registration of a READ command and the availability

of the first piece of output data. The latency can be set to

two or three clocks.

If a READ command is registered at clock edge n, and

the latency is m clocks, the data will be available by clock

edge n+m. The I/Os will start driving as a result of the clock

edge one cycle earlier (n + m - 1), and provided that the

relevant access times are met, the data will be valid by

clock edge n + m. For example, assuming that the clock

cycle time is such that all relevant access times are met,

if a READ command is registered at T0 and the latency is

programmed to two clocks, the I/Os will start driving after

T1 and the data will be valid by T2. Table 2 below indicates

the operating frequencies at which each CAS latency setting

can be used.

Reserved states should not be used as unknown operation