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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

WEDPN8M72V-XB2X

White Electronic Designs

January 2005

Rev. 4

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

AC FUNCTIONAL CHARACTERISTICS (NOTES 5,6,7,8,9,11)

Parameter/Condition

Symbol

-100

-125

-133

Units

READ/WRITE command to READ/WRITE command (17)

111

CKE to clock disable or power-down entry mode (14)

1

1

1

CKE to clock enable or power-down exit setup mode (14)

111

DQM to input data delay (17)

0

0

0

DQM to data mask during WRITEs

0

0

0

DQM to data high-impedance during READs

2

2

2

WRITE command to input data delay (17)

0

0

0

Data-in to ACTIVE command (15)

455

Data-in to PRECHARGE command (16)

2

2

2

Last data-in to burst STOP command (17)

111

Last data-in to new READ/WRITE command (17)

1

1

1

Last data-in to PRECHARGE command (16)

2

2

2

LOAD MODE REGISTER command to ACTIVE or REFRESH command (25)

222

Data-out to high-impedance from PRECHARGE command (17)

CL = 3

333

CL = 2

2—

—

NOTES:

minimum cycle time and the outputs open.

4. Enables on-chip refresh and address counters.

5. The minimum specifications are used only to indicate cycle time at which proper

operation over the full temperature range is ensured.

6. An initial pause of 100ms is required after power-up, followed by two AUTO REFRESH

commands, before proper device operation is ensured. The two AUTO REFRESH

command wake-ups should be repeated any time the tREF refresh requirement is

exceeded.

8. In addition to meeting the transition rate specification, the clock and CKE must transit

9. Outputs measured at 1.5V with equivalent load:

crossover point.

12. Other input signals are allowed to transition no more than once every two clocks and

cycle rate.

minimum cycle rate.

17. Required clocks are specified by JEDEC functionality and are not dependent on any

timing parameter.

that the maximum cycle rate is slower as the CAS latency is reduced.

19. Address transitions average one transition every two clocks.

20. CLK must be toggled a minimum of two times during this period.

pulse width ≤ 3ns.

22. The clock frequency must remain constant (stable clock is defined as a signal cycling

within timing constraints specified for the clock pin) during access or precharge states

(READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to

reduce the data rate.

the first clock delay, after the last WRITE is executed.

24. Precharge mode only.

25. JEDEC and PC100 specify three clocks.

26. Parameter guaranteed by design.

27. Self refresh available in commercial and industrial temperatures only.

Q

1.5V

50Ω