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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

WEDPZ512K72V-XBX

February 2006

Rev. 7

OUTPUT LOAD (A)

OUTPUT LOAD (B)

FOR tlzc, tlzoe, thzoe, and thzc

Dout

Zo=50Ω

RL=50Ω

VL=1.5V

50pF*

Dout

353Ω/1538Ω

5pF*

+3.3V for 3.3V I/O, +2.5V for 2.5V I/O

319Ω/1667Ω

*Including Scope and Jig Capacitance

AC TEST CONDITIONS

Parameter

Value

Input Pulse Level

0 to 3.6V

Input Rise and Fall Time

1.0V/ns

Input and Output Timing Reference Levels

1.5V

Output Load

See Output Load (A & B)

AC CHARACTERISTICS

Parameter

Symbol

150MHz

133MHz

100MHz

Units

Min

Max

Min

Max

Min

Max

Clock Time

6.7

7.5

10.0

ns

Clock Access Time

—

3.8

—

4.2

—

5.0

ns

Output enable to Data Valid

—

3.8

—

4.2

—

5.0

ns

Clock High to Output Low-Z

1.5

—

1.5

—

1.5

—

ns

Output Hold from Clock High

1.5

—

1.5

—

1.5

—

ns

Output Enable Low to output Low-Z

0.0

—

0.0

—

0.0

—

ns

Output Enable High to Output High-Z

—

3.0

—

3.5

—

3.5

ns

Clock High to Output High-Z

—

3.0

—

3.5

—

3.5

ns

Clock High Pulse Width

2.5

—

2.5

—

3.0

—

ns

Clock Low Pulse Width

2.5

—

2.5

—

3.0

—

ns

Address Setup to Clock High

1.5

—

1.5

—

1.5

—

ns

CKE Setup to Clock High

1.5

—

1.5

—

1.5

—

ns

Data Setup to Clock High

1.5

—

1.5

—

1.5

—

ns

Write Setup to Clock High

1.5

—

1.5

—

1.5

—

ns

Address Advance to Clock High

1.5

1.5

1.5

ns

Chip Select Setup to Clock High

1.5

1.5

1.5

ns

Address Hold to Clock high

0.5

—

0.5

—

0.5

—

ns

CKE Hold to Clock High

0.5

-

0.5

—

0.5

—

ns

Data Hold to Clock High

0.5

—

0.5

—

0.5

—

ns

Write Hold to Clock High

0.5

—

0.5

—

0.5

—

ns

Address Advance to Clock High

0.5

—

0.5

—

0.5

—

ns

Chip Select Hold to Clock High

0.5

—

0.5

—

0.5

—

ns

NOTES:

1.

All Address inputs must meet the specified setup and hold times for all rising clock (CLK) edges when ADV is sampled low and CSx# is

sampled valid. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.

2.

Chip enable must be valid at each rising edge of CLK (when ADV is Low) to remain enabled.

3.

A write cycle is defined by WE# low having been registered into the device at ADV Low. A Read cycle is defined by WE# High with ADV Low.

Both cases must meet setup and hold times.