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WME128K8-150DEQ Datasheet(PDF) 7 Page - White Electronic Designs Corporation

Part # WME128K8-150DEQ
Description  128Kx8 CMOS MONOLITHIC EEPROM, SMD 5962-96796
Download  11 Pages
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Manufacturer  WEDC [White Electronic Designs Corporation]
Direct Link  http://www.whiteedc.com
Logo WEDC - White Electronic Designs Corporation

WME128K8-150DEQ Datasheet(HTML) 7 Page - White Electronic Designs Corporation

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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WME128K8-XXX
January 2004
Rev. 5
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
PAGE WRITE OPERATION
The WME128K8-XXX has a page write operation that
allows one to 128 bytes of data to be written into the device
and consecutively loads during the internal programming
period. Successive bytes may be loaded in the same
manner after the first data byte has been loaded. An
internal timer begins a time out operation at each write
cycle. If another write cycle is completed within 150µs
or less, a new time out period begins. Each write cycle
restarts the delay period. The write cycles can be continued
as long as the interval is less than the time out period.
The usual procedure is to increment the least significant
address lines from A0 through A6 at each write cycle. In
this manner a page of up to 128 bytes can be loaded in
to the EEPROM in a burst mode before beginning the
relatively long interval programming cycle.
After the 150µs time out is completed, the EEPROM
begins an internal write cycle. During this cycle the entire
page of bytes will be written at the same time. The internal
programming cycle is the same regardless of the number
of bytes accessed.
FIGURE 7 – PAGE MODE WRITE WAVEFORMS
PAGE WRITE CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Page Mode Write Characteristics
Symbol
Unit
Parameter
Min
Max
Write Cycle Time, TYP = 6ms
twc
10
ms
Address Set-up Time
tas
10
ns
Address Hold Time (1)
tah
100
ns
Data Set-up Time
tds
50
ns
Data Hold Time
tdh
10
ns
Write Pulse Width
twp
100
ns
Byte Load Cycle Time
tblc
150
µs
Write Pulse Width High
twph
50
ns
1. Page address must remain valid for duration of write cycle.
OE#
BYTE 0
BYTE 1
BYTE 2
BYTE 3
VALID DATA
VALID
ADDRESS
t WC
t BLC
t WPH
t WP
ADDRESS
DATA
CS#
WE#
BYTE 127
t DS
t DH
t AS
t AH


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