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WME128K8-150DEM Datasheet(PDF) 3 Page - White Electronic Designs Corporation |
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WME128K8-150DEM Datasheet(HTML) 3 Page - White Electronic Designs Corporation |
3 / 11 page 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WME128K8-XXX January 2004 Rev. 5 White Electronic Designs Corp. reserves the right to change products or specifications without notice. READ Figure 3 shows Read cycle waveforms. A read cycle begins with selection address, chip select and output enable. Chip select is accomplished by placing the CS# line low. Output enable is done by placing the OE# line low. The memory places the selected data byte on I/O0 through I/O7 after the access time. The output of the memory is placed in a high impedance state shortly after either the OE# line or CS# line is returned to a high level. FIGURE 3 – READ WAVEFORMS t ADDRESS CS# OE# OUTPUT OH tDF t ACC t RC t OE tACS OUTPUT VALID ADDRESS VALID HIGH Z NOTE: OE# may be delayed up to tACS- tOE after the falling edge of CS# without impact on tOE or by tACC- tOE after an address change without impact on tACC. AC READ CHARACTERISTICS (See Figure 3) VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C Read Cycle Parameter Symbol -120 -140 -150 -200 -250 -300 Unit Min Max Min Max Min Max Min Max Min Max Min Max Read Cycle Time tRC 120 140 150 200 250 300 ns Address Access Time tACC 120 140 150 200 250 300 ns Chip Select Access Time tACS 120 140 150 200 250 300 ns Output Hold from Address Change, OE# or CS# tOH 000000 ns Output Enable to Output Valid tOE 050055055055085085 ns Chip Select or OE# to High Z Output tDF 60 70 70 70 70 70 ns |
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