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WED7G1G5IDE36ADC25 Datasheet(PDF) 3 Page - White Electronic Designs Corporation |
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WED7G1G5IDE36ADC25 Datasheet(HTML) 3 Page - White Electronic Designs Corporation |
3 / 8 page 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED7GxxxIDE36 WED7GxxxIDE33 July, 2003 Rev. 0 PRELIMINARY* White Electronic Designs Corp. reserves the right to change products or specifications without notice. SIGNAL NAME DIR PIN DESCRIPTION RESET I 100 HOST RESET. Reset signal from the host that is active on power up. D(15-0) I/O 70,62,54,46,38,30, 22,14,10,18,26,34, 42,50,58,66 HOST DATA. These 16 lines carry the data between the controller and the host. The low 8 lines transfer commands, status and ECC information between the host and the controller. IOWR I 84 I/O WRITE. This strobe pulse is used to clock data or commands on the host data bus into the controller. The clocking will occur on the negative to positive edge of the signal (trailing edge). IORD I 82 I/O READ. This is a read strobe generated by the host. This signal gates data or status on the host bus and strobes the data from the controller into the host on the low to high transition (trailing edge). CSEL I 98 This internally pulled up signal is used to configure this device as a Master or a Slave. When this pin is grounded by the host, this device is configured as a Master. When this pin is high (or open), this device is configured as a Slave. IRQ O 96 INTERRUPT REQUEST. This is an interrupt request from the controller to the host, asking for service. The output of this signal is tri-stated when the interrupts are disabled by the host. IOCS16 O 124 I/O SELECT 16. This open drain output is asserted low by the controller to indicate to the host the current cycle is a16 bit word data transfer. PDIAG I/O 118 PASS DIAGNOSTIC. This bi-directional open drain signal is asserted by the slave after anExecute Diagnostic command to indicate to the master it has passed its diagnostics. A(2-0) I 110,120,122 HOST ADDRESS. These address lines are used to select the registers within the controller task file. CS0 I 74 HOST CHIP SELECT 0. This is a chip select signal that is used to select the controller task file. CS1 I 80 HOST CHIP SELECT 1. This is a chip select signal that is used to select the control and diagnostic register. DASP I/O 116 DISK ACTIVE/SLAVE PRESENT. This open drain output signal is asserted low any time the drive is active. In a master/slave configuration, this signal is used by the slave to inform the master a slave is present. IORDY O 102 This is an optional signal that is negated when the drive is not ready to respond to a data transfer request. For the module this signal is not used, the pin is pulled up. As long as the host obeys PIO mode 0 or 4 timing, the module is guaranteed to respond properly. GND 2,6,128 GROUND. Vcc 4,126 POWER (3.3V – 5V) SIGNAL DESCRIPTION |
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