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WMS256K16L-20DLI Datasheet(PDF) 3 Page - White Electronic Designs Corporation |
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WMS256K16L-20DLI Datasheet(HTML) 3 Page - White Electronic Designs Corporation |
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3 / 7 page  WMS256K16-XXX 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs August 2004 Rev. 6 I Current Source D.U.T. C = 50 pf eff I OL V ≈ 1.5V (Bipolar Supply) Z Current Source OH Notes: Vz is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75 Ω. Vz is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance. AC TEST CIRCUIT AC TEST CONDITIONS Parameter Typ Unit Input Pulse Levels VIL = 0, VIH = 3.0 V Input Rise and Fall 5 ns Input and Output Reference Level 1.5 V Output Timing Reference Level 1.5 V AC CHARACTERISTICS VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C Parameter Write Cycle Symbol -17 -20 -25 -35 Units Min Max Min Max Min Max Min Max Write Cycle Time tWC 17 20 25 35 ns Chip Select to End of Write tCW 14 17 20 25 ns Address Valid to End of Write tAW 14 17 20 25 ns Data Valid to End of Write tDW 10 12 15 20 ns Write Pulse Width tWP 14 17 20 25 ns Address Setup Time tAS 0000 ns Address Hold Time tAH 2222 ns Output Active from End of Write tOW1 0000 ns Write Enable to Output in High Z tWHZ1 9 101015 ns Data Hold Time tDH 0000 ns LB#, UB# Valid to End of Write tBW 14 17 20 25 ns 1. This parameter is guaranteed by design but not tested. AC CHARACTERISTICS VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C Parameter Read Cycle Symbol -17 -20 -25 -35 Units Min Max Min Max Min Max Min Max Read Cycle Time tRC 17 20 25 35 ns Address Access Time tAA 17 20 25 35 ns Output Hold from Address Change tOH 0000 ns Chip Select Access Time tACS 17 20 25 35 ns Output Enable to Output Valid tOE 10 12 15 20 ns Chip Select to Output in Low Z tCLZ1 2555 ns Output Enable to Output in Low Z tOLZ1 0000 ns Chip Disable to Output in High Z tCHZ1 9 101215 ns Output Disable to Output in High Z tOHZ1 9 101215 ns LB#, UB# Access Time tBA 10 12 14 17 ns LB#, UB# Enable to Low Z Output tBLZ1 0000 ns LB#, UB# Disable to High Z Output tBHZ1 9 101215 ns 1. This parameter is guaranteed by design but not tested. |
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