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WE128K32N-150G2TIA Datasheet(PDF) 6 Page - White Electronic Designs Corporation |
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WE128K32N-150G2TIA Datasheet(HTML) 6 Page - White Electronic Designs Corporation |
6 / 14 page 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WE128K32-XXX March 2006 Rev. 10 White Electronic Designs Corp. reserves the right to change products or specifications without notice. READ The WE128K32-XXX stores data at the memory location determined by the address pins. When CS# and OE# are low and WE# is high, this data is present on the outputs. When CS# and OE# are high, the outputs are in a high impedance state. This two line control prevents bus contention. Notes: OE# may be delayed up to tACS - tOE after the falling edge of CS# without impact on tOE or by tACC - tOE after an address change without impact on tACC. AC READ CHARACTERISTICS VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C Read Cycle Parameter Symbol -120 -140 -150 -200 -250 -300 Unit Min Max Min Max Min Max Min Max Min Max Min Max Read Cycle Time tRC 120 140 150 200 250 300 ns Address Access Time tACC 120 140 150 200 250 300 ns Chip Select Access Time tACS 120 140 150 200 250 300 ns Output Hold from Add. Change, OE# or CS# tOH 000000 ns Output Enable to Output Valid tOE 050055055055085085 ns Chip Select or OE# to High Z Output tDF 60 70 70 70 70 70 ns FIGURE 7 – READ WAVEFORMS t ADDRESS CS# OE# OUTPUT OH tDF t ACC t RC t OE tACS OUTPUT VALID ADDRESS VALID HIGH Z |
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