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WV3EG32M64ETSU-D3 Datasheet(PDF) 5 Page - White Electronic Designs Corporation |
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WV3EG32M64ETSU-D3 Datasheet(HTML) 5 Page - White Electronic Designs Corporation |
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5 / 12 page  White Electronic Designs 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com July 2005 Rev. 0 ADVANCED WV3EG32M64ETSU-D3 IDD SPECIFICATIONS AND TEST CONDITIONS 0°C ≤ TA ≤ 70°C, VCC = VCCQ = 2.5V ± 0.2V Includes DDR SDRAM component only Parameter Symbol Conditions DDR333@ CL = 2.5 Units Operating one bank active- precharge current; IDD0 tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING 720 mA Operating one bank active- read-precharge current; IDD1 IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS is HIGH between valid commands; Address businputs are SWITCHING; Data pattern is same as IDD4W 920 mA Precharge power-down current; IDD2P All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING 24 mA Precharge quiet standby current; IDD2Q All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputsare STABLE; Data bus inputs are FLOATING 160 mA Precharge standby current; IDD2F All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING 200 mA Active power-down current; IDD3P All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING 280 mA Active standby current; IDD3N All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS - is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING 440 mA Operating burst write current; IDD4W All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRAS-max(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING 1280 mA Operating burst read current; IDD4R All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W 1280 mA Burst auto refresh current; IDD5 tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING 1360 mA Self refresh current; IDD6 CK and CK at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING 24 mA Operating bank interleave read current; IDD7 All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)- 1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the following page for detailed timing conditions 2240 mA Note: These specifications apply to modules built with Samsung components only. |
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