WV3HG128M72EER665D7IMG datasheet(6/11 Pages) WEDC

Part #	WV3HG128M72EER665D7IMG

Description	1GB - 128Mx72 DDR2 SDRAM REGISTERED, w/PLL, Mini-DIMM

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Manufacturer	WEDC [White Electronic Designs Corporation]

Direct Link	http://www.whiteedc.com

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WV3HG128M72EER-D7

May 2006

Rev. 0

ADVANCED

6

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

DDR2 ICC SPECIFICATIONS AND CONDITIONS

VCC = +1.8V ± 0.1V

Symbol

Parameter

Condition

806

665

534

403

Unit

ICC0*

Operating

one bank

active-

precharge;

tCK = tCK(I

CC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid

commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

TBD

1,210

1,165

1,120

mA

ICC1*

Operating

one bank

active-

read-

precharge;

IOUT = 0mA; BL = 4; CL = CL(ICC); tCK = tCK(I

CC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is

HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING; Data pattern is same as ICC4W.

TBD

1,300

1,255

1,210

mA

ICC2P**

Precharge

power-

down

current;

All banks idle; tCK = tCK(I

CC); CKE is LOW; Other control and address bus inputs are

STABLE; Data bus inputs are FLOATING

TBD

508

mA

ICC2Q**

Precharge

quite

standby

current;

All banks idle; tCK = tCK(I

CC); CKE is HIGH; CS# is HIGH; Other control and address bus

inputs are STABLE; Data bus inputs are FLOATING

TBD

760

715

mA

ICC2N**

Precharge

standby

current;

All banks idle; tCK = tCK(I

CC); CKE is HIGH; CS# is HIGH; Other control and address bus

inputs are STABLE; Data bus inputs are SWITCHING

TBD

805

760

mA

ICC3P**

Active

power-

down

current;

All banks open; tCK = tCK(I

CC), CKE is LOW; Other control

and address bus inputs are STABLE; Data bus inputs are

FLOATING

Fast PDN Exit

MRS(12) = 0

TBD

670

625

mA

Slow PDN Exit

MRS(12) = 1

TBD

508

mA

ICC3N**

Active

standby

current;

All banks open; tCK = tCK(I

CC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS#

is HIGH between valid commands; Other control and address bus inputs are

SWITCHING; Data bus inputs are SWITCHING

TBD

850

805

mA

ICC4W*

Operating

burst write

current;

All banks open; Continuous burst writes; BL = 4; CL = CL(ICC); AL = 0; tCK = tCK(I

CC);

tRC = tRC(I

CC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

TBD

1,795

1,570

1,435

mA

ICC4R*

Operating

burst read

current;

All banks open; Continuous burst reads; TOUT = 0mA; BL = 4; CL = CL(ICC); AL = 0;

tCK = tCK(I

CC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is HIGH between

valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W.

TBD

1,795

1,570

1,435

mA

ICC5**

Burst auto

refresh

current;

tCK = tCK(I

CC); Refresh command at every tRC(ICC) interval; CKE is HIGH; CS# is HIGH

between valid commands; Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

TBD

2,380

2,335

2,290

mA

ICC6**

Self

refresh

current;

CK and CK# at 0V; CKE < 0.2V; Other control and address bus

inputs are FLOATING; Data bus inputs are FLOATING

Normal

TBD

90

mA

ICC7*

Operating

bank

interleave

read

current;

All bank interleaving reads; IOUT = 0mA; BL = 4; CL = CL(ICC); AL = tRCD(I

CC) - 1*tCK(ICC);

tCK = tCK(I

CC); tRC = tRC(ICC); tRRD = tRRD MIN(ICC) = 1*tCK(ICC); CKE is HIGH; CS# is HIGH

between valid commands; Address bus inputs are STABLE during DESELECTs; Data

bus inputs are SWITCHING

TBD

3,100

2,920

2,740

mA

Notes:

ICC speciﬁcation is based on SAMSUNG components. Other DRAM manufacturers speciﬁcation may be different.

* Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P ( CKE LOW) mode.

** Value calculated reﬂects all module ranks in this operating condition.

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