 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
V3022SO28B Datasheet(PDF) 9 Page - EM Microelectronic - MARIN SA |
|
||||||||||||||||||||||||||||||
V3022SO28B Datasheet(HTML) 9 Page - EM Microelectronic - MARIN SA |
|
|
9 / 15 page  R V3022 Copyright © 2004, EM Microelectronic-Marin SA 9 www.emmicroelectronic.com Status Words Table 6 Table 7 Table 8 Address Command Space This space contains the three commands used for carrying out the transfers between the Time and Data Register and / or the Timer Registers and the reserved clock and timer area. RAM Map Address Parameter Range Dec Hex Data Space Status 00 00 status 0 01 01 status 1 02 02 status 2 Special purpose 16 10 digital trimming 0-255 Clock 32 20 1/100 second 00-99 33 21 seconds 00-59 34 22 minutes 00-59 35 23 hours (note 1) 00-23 36 24 date 01-31 37 25 month 01-12 38 26 year 00-99 39 27 week day 01-07 40 28 week number 00-53 Alarm 48 30 1/100 second 00-99 49 31 seconds 00-59 50 32 minutes 00-59 51 33 hours (note 1 & 2) 00-23 52 34 date 01-31 Timer 64 40 1/100 second 00-99 65 41 seconds 00-59 66 42 minutes 00-59 67 43 hours 00-23 Address Command Space 240 F0 clock and timer transfer 241 F1 clock transfer 242 F2 timer transfer Table 9 Note 1 : The MSB (bit 7) of the hours byte (addr. 23 hex for the clock and 33 hex for the alarm) are used as AM/PM indicators in the 12 hour time data format and reading of the hours byte must be preceded by masking of the AM/PM bit. A set AM/PM bit indicates PM. In the 24 hour time data format the bit will always be zero. Note 2 : The alarm hours, addr. 33 hex, must always be rewritten after a change between 12 and 24 hour modes. Communication Data transfer is in 8 bit parallel form. All time data is in packed BCD format with tens data on lines AD7-4 and units on lines AD3-0. To access information within the RAM (see Fig.7) first write the RAM address, then read or write from or to this location. Fig.8 shows the two steps needed. The lines AD0-7 will be treated as an address when pin A /D is low, and as data when A /D is high. Pin A /D must not change state during any single read or write access. One line of the address bus (e.g. A0) can be used to implement the A /D signal (see "Typical Operating Configuration", Fig.1). Until a new address is written, data accesses (/D high) will always be to the same RAM address. |
Similar Part No. - V3022SO28B |
|
Similar Description - V3022SO28B |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
