W183
Document #: 38-07158 Rev. *A
Page 7 of 9
Application Information
Recommended Circuit Configuration
For optimum performance in system applications the power
supply decoupling scheme shown in Figure 4 should be used.
VDD decoupling is important to both reduce phase jitter and
EMI radiation. The 0.1-
µF decoupling capacitor should be
placed as close to the VDD pin as possible, otherwise the in-
creased trace inductance will negate its decoupling capability.
The 10-
µF decoupling capacitor shown should be a tantalum
type. For further EMI protection, the VDD connection can be
made via a ferrite bead, as shown.
Recommended Board Layout
Figure 5 shows a recommended a 2-layer board layout
Figure 4. Recommended Circuit Configuration
GND
14
13
12
11
1
2
3
4
C1
FB
C2
3.3V or 5V System Supply
10 µF Tantalum
0.1 µF
Clock
Output
R1
10
9
8
5
6
7
C3
0.1 µF
Xtal Connection or NC
Xtal Connection or Reference Input
Clock Output
High frequency supply decoupling
capacitor (0.1-µF recommended).
Common supply low frequency
decoupling capacitor (10-µF tantalum
recommended).
FB
Ferrite Bead
C1, C3 =
C2 =
Match value to line impedance
R1 =
=
R1
C1
C2
G
G
FB
= Via To GND Plane
G
NC
G
(3.3V or 5V)
C3
G
Power Supply Input
Xtal Connection or Reference Input
G
Xtal Connection or
Figure 5. Recommended Board Layout (2-Layer Board)
Ordering Information
Ordering Code
Package
Name
Package Type
W183
W183-5
G
14-Pin Plastic SOIC (150-mil)
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
