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V3023SO28A Datasheet(PDF) 4 Page - EM Microelectronic - MARIN SA |
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V3023SO28A Datasheet(HTML) 4 Page - EM Microelectronic - MARIN SA |
4 / 15 page R V3023 Copyright © 2004, EM Microelectronic-Marin SA 4 www.emmicroelectronic.com Timing Characteristics (standard temperature range) VDD= 5.0 ±10%, VSS = 0V and TA=-40 to +85°C Parameter Symbol Test Conditions Min. Typ. Max. Unit Chip select duration, write cycle tCS 50 ns Write pulse duration tWR 50 ns Time between two transfers tW 100 ns RAM access time (note 1) tACC CLOAD = 50pF 50 60 ns Data valid to Hi-impedance (note 2) tDF 10 30 40 ns Write data settle time (note 3) tDW 50 ns Data hold time (note 4) tDH 10 ns Advance write time tADW 10 ns PF response delay tPF 100 ns Rise time (all timing waveform signals) tR 200 ns Fall time (all timing waveform signals) tF 200 ns CS delay after A /D (note 5) t A /Ds 5 ns CS delay to A /D t A /Dt 10 ns Table 4 Note 1 : tACC starts from RD ( DS ) or CS , whichever activates last Typically, tACC = 5 + 0.9 CEXT in ns; where CEXT (external parasitic capacitance) is in pF Note 2 : tDF starts from RD ( DS ) or CS , whichever deactivates first Note 3 : tDW ends at WR (R/ W ) or CS , whichever deactivates first Note 4 : tDH starts from WR (R/ W ) or CS , whichever deactivates first Note 5 : A /D must come before a CS and RD or a CS and WR combination. The user has to guarantee this. Timing Waveforms Read Timing for Intel ( RD and WR Pulse) and Motorola ( DS or RD pin tied to CS and R/ W ) Fig. 6a |
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