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EM6625TQ52B Datasheet(PDF) 10 Page - EM Microelectronic - MARIN SA |
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EM6625TQ52B Datasheet(HTML) 10 Page - EM Microelectronic - MARIN SA |
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10 / 69 page  R EM6625 Copyright © 2005, EM Microelectronic-Marin SA 10 www.emmicroelectronic.com 4.4 Digital Watchdog Timer Reset The digital watchdog is a simple, non-programmable, 2-bit timer, that counts on each rising edge of Ck[1]. It will generate a system reset if it is not periodically cleared. The watchdog timer function can be inhibited by activating an inhibit digital watchdog bit (NoLogicWD) located in RegVldCntl. At power up, and after any system reset, the watchdog timer is activated. If for any reason the CPU stops, then the watchdog timer can detect this situation and activate the system reset signal. This function can be used to detect program overrun, endless loops, etc. For normal operation, the watchdog timer must be reset periodically by software at least every 2.5 seconds (system clock = 32 KHz), or a system reset signal is generated. The watchdog timer is reset by writing a ‘1’ to the WDReset bit in the timer. This resets the timer to zero and timer operation restarts immediately. When a ‘0’ is written to WDReset there is no effect. The watchdog timer operates also in the standby mode and thus, to avoid a system reset, one should not remain in standby mode for more than 2.5 seconds. From a system reset state, the watchdog timer will become active after 3.5 seconds. However, if the watchdog timer is influenced from other sources (i.e. prescaler reset), then it could become active after just 2.5 seconds. It is therefore recommended to use the Prescaler IRQHz1 interrupt to periodically reset the watchdog every second. It is possible to read the current status of the watchdog timer in RegSysCntl2. After watchdog reset, the counting sequence is (on each rising edge of CK[1]) : ‘00’, ‘01’, ‘10’, ‘11’ {WDVal1 WDVal0}. When going into the ‘11’ state, the watchdog reset will be active within ½ second. The watchdog reset activates the system reset which in turn resets the watchdog. If the watchdog is inhibited it’s timer is reset and therefore always reads ‘0’. Table 4.4.1 Watchdog Timer Register RegSysCntl2 Bit Name Reset R/W Description 3 WDReset 0 R/W Reset the Watchdog 1 -> Resets the Logic Watchdog 0 -> No action The Read value is always '0' 2 SleepEn 0 R/W See Operating modes (sleep) 1 WDVal1 0 R Watchdog timer data Ck[1] divided by 4 0 WDVal0 0 R Watchdog timer data Ck[1] divided by 2 4.5 CPU State after Reset Reset initializes the CPU as shown in Table 4.5.1 below. Table 4.5.1 Initial CPU Value after Reset. Name Bits Symbol Initial Value Program counter 0 12 PC0 hex 000 (as a result of Jump 0) Program counter 1 12 PC1 Undefined Program counter 2 12 PC2 Undefined Stack pointer 2 SP PSP[0] selected Index register 7 IX Undefined Carry flag 1 CY Undefined Zero flag 1 Z Undefined Halt 1 HALT 0 Instruction register 16 IR Jump 0 Periphery registers 4 Reg. See peripheral memory map |
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