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EM6635 Datasheet(PDF) 2 Page - EM Microelectronic - MARIN SA |
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EM6635 Datasheet(HTML) 2 Page - EM Microelectronic - MARIN SA |
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2 / 39 page  EM6635 03/03 REV.B Copyright 2002, EM Microelectronic-Marin SA 2 www.emmicroelectronic.com EM6635 at a glance Power Supply - Low voltage low power architecture - including internal voltage regulator - 1.2 to 3.6 V battery voltage - 1.5µA in active mode (Xtal, 25 °C) - 0.4 µA in HALT mode (Xtal, 25 °C) - 32’768Hz Crystal Oscillator - 500kHz RC oscillator (no external component) - External clock (metal option) RAM - 4 pages of 64 x 4bits, page 0 is direct addressable ROM - 4096 x 16bits, metal mask programmable CPU - 4-bits RISC architecture - 2 clock cycles per instruction (CPI=2) - 72 basic instructions - operating frequency selectable by SW Main Operating Modes and Resets - Active mode, CPU is running - Halt mode, CPU in halt, peripheral are running - Initial reset on power on (POR) - Watchdog reset (logic) - Reset terminal with Schmitt Trigger - Reset with input combination on Port P1 & Port P2 (register selectable) Prescaler - 15 stage system clock divider from 32kHz down to 1Hz - 4 Interrupt requests; 128Hz, 64Hz, 32Hz and 1Hz or 64Hz, 16Hz, 8Hz and 1Hz - Prescaler state readable to CPU from 128Hz to 16Hz and from 8Hz to 1Hz - Prescaler reset (32Hz to 1Hz) 8bit Serial Interface at Port 5 - 4 wire (serial clock In/Out, serial output, serial status In/Out (RDY), serial input) - Master mode: 32kHz, 16kHz or 4kHz serial clock - Slave mode: external clock from P33 - Selectable word length: 8 - 7 - 6 - 5 bit - Selectable synchronized or direct output - Selectable positive or negative active clock edge by direct or inverted serial clock SCK - Special ready output mode when port is in master mode - RDY can be set by SW Frequency Generator with 255 output frequencies - 8bit programmable frequency divider - 50% duty cycle output signal - Clock frequency is 65536Hz (doubled 32768Hz) - SW activated Watchdog Timer - Creates watchdog reset after time-out - Can be disabled by SW and mask option Interrupt Controller - 12 internal, 6 external interrupt request sources - Individually maskable, individually resettable - Global interrupts disable,with auto-enable at HALT mode Voltage Level Detector (SVLD) - 3 software selectable levels - Busy flag during measure - Active only on request during measurement to reduce power consumption Timer 1 - 8bits timer with 3 modes: Zero Stop, Synchron Mode and Auto Reload Mode - Timer clock selectable 4kHz-2kHz-1kHz-512Hz by SW - Zero Stop: Timer starts counting down when loaded from CPU with data (> 0). When at zero, an interrupt is generated. - Synchron Mode: After loading by CPU, timer starts synchronized by the positive edge of the prescaler 64Hz signal. An interrupt is generated when timer reaches zero. During timer count down, Port P3 and P4 are outputting their data, otherwise P3 and P4 are at high level (acc. to selected port configuration). - Auto Reload Mode: (see text at Timer 2) Timer 2 - 8bits timer with 2 modes: Zero Stop and Auto Reload - Zero Stop as timer1 - Auto Reload mode: Timer starts when a non-zero data is loaded by CPU and counts down to zero. Then the loaded data (internally stored) is automatically reload to the timer counter and the sequence starts again. Each time when zero is reached, an interrupt is generated. - Timer clock selectable 256Hz-64Hz-16Hz-4Hz by SW CHRONO 2x4bits BCD counters - Start, stop, reset by SW - 1/100th second resolution - CARRY flag can be read by SW when the counter changes from 99 to 0 Event Counter 3bits - Associated to input port P10, P11; readable to CPU - Counter counts up to 7 and stays there - Counter reset by CPU-write Buzzer Output - Piezo driver via external NPN transistor - Activated together with frequency generator Input Ports P1, P2 - Direct or debounced input read selectable by SW for each port - Clocked pulldown or no pulldown by mask option - P1: Edge detector at P10, P11 (both edges) to generate pulse for event counter - Interrupt by P12: both edges, by P13: both edges - Interrupt by positive edge (debounced) of any P2 input - Reset by debounced input combination: P13, P22, P23 = high, enabled by SW Input / Output Ports P3, P4, P5, P6, P7 - High current drive capability at P3, P4 and P72 - P3, P4: Common direction select P30-P32, P40-P42; P33 and P43 are individually selectable - P5: individual direction select, debouncer when input - As input: direct read of terminal data, as output: register data - P3,P4,P72: selectable 9,8,7,6,5,4 or 3 high drive output in combination with special synchron mode of timer 1 - P5: pull down / pull up according to mask option - P6: As input: Direct or debounced input read selectable by SW - Interrupt by positive edge (debounced) of any P6 input - Common direction select P60-P61, P62-P63 - P70, P71: As input: Direct or debounced input read selectable by SW for each port - Interrupt by positive edge (debounced) of P70, P71 input - Common direction select P70, P71 |
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