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EM6680WS11 Datasheet(PDF) 6 Page - EM Microelectronic - MARIN SA |
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EM6680WS11 Datasheet(HTML) 6 Page - EM Microelectronic - MARIN SA |
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6 / 58 page  R EM6680 Copyright © 2005, EM Microelectronic-Marin SA 6 www.emmicroelectronic.com Table 2.3.1 Shows the Status of different EM6680 blocks in these three main operating modes. Peripheral /// EM6680 mode ACTIVE mode STAND-BY mode SLEEP mode POR (static) On On On Voltage regulator On On On (Low-Power) RC-oscillator On On Off Clocks (Prescaler & RC divider) On On Off CPU Running In HALT – Stopped Stopped Peripheral register “On” “On” retain value retain value RAM “On” retain value retain value Timer/Counter “On” “On” if activated before stopped Supply Voltage Level Det.=SVLD can be activated “On” if activated before Off PortA / Reset pad debounced Yes Yes No Interrupts / events Yes - possible Yes - possible No – not possible Watch-Dog timer On / Off (soft selectable) On / Off (soft selectable) No Wake Up on Change PortA No No On/Off (soft select.) Sleep Reset Counter Off Off On/Off (soft select.) 3. Power Supply The EM6680 is supplied by a single external power supply between Vdd (VBAT) and VSS (ground). A built-in voltage regulator generates Vreg providing regulated voltage for the oscillator and the internal logic. The output drivers are supplied directly from the external supply VDD. Internal power configuration is shown in Figure 3 and Figure 4. To supply the internal core logic it is possible to use either the internal voltage regulator (Vreg < VDD) or directly ( Vreg = VDD). The selection is done by metal 1 mask option. By default the voltage regulator is used. Refer to chapter 88H88H 0 for the metal mask selection. The internal voltage regulator is chosen for high voltage systems. It saves power by reducing the internal core logic’s power supply to an optimum value. However, due to the inherent voltage drop over the regulator the minimal VDD value is restricted to 1.4V . A direct VDD connection can be selected for systems running on a 1.5V battery. The 1k Ω resistor together with the external capacitor on Vreg is filtering the Vdd supply to the internal core. In this case the minimum VDD value can be as low as 1.2 V. |
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