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EM6640WP27 Datasheet(PDF) 10 Page - EM Microelectronic - MARIN SA |
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EM6640WP27 Datasheet(HTML) 10 Page - EM Microelectronic - MARIN SA |
10 / 62 page EM6640 03/02 REV. C/446 Copyright 2002, EM Microelectronic-Marin SA 10 www.emmicroelectronic.com 4.4 Sleep Counter Reset (SCR) The Sleep Counter Reset, active only in SLEEP mode, will automatically trigger a reset which cancels Sleep Mode after a programmable time defined by writing bit RstSlpTSel[2:0] in option register OptSlpCntRst. The EnSlpCntRst bit in option register OptSlpCntRst set to "1" will enable the SCR as soon as the SLEEP bit in RegSysCntl1 is written active. In this case, all the sleep considerations (low consumption) are taken into account (refer to chapter SLEEP Mode, page 5 for more details). When the SCR generates a reset, the CPU reset is removed after the ‘CPU Reset Delay’. The typical time constant of SCR is defined in the section EM6640 Electrical specifications, on page 55. => The minimum programmable time is 1x the time constant. => The maximum programmable time is 128x the time constant. Figure 9 Sleep Counter Reset representation with SCR timing=2x as an example. Sy sC lk S leep SCR CPU re se t S C R tim ing = 2x CP U Rst De la y ac tiv e m ode activ e m ode S leep m ode Table 10 register OptSlpCntRst Bit Name Reset R/W Description 3 EnSlpCntRst 0 R/W enable SCR 2 RstSlpTSel[2] 0 R/W timing selection 1 RstSlpTSel[1] 0 R/W timing selection 0 RstSlpTSel[0] 0 R/W timing selection Table 11 Sleep Counter Reset timing RstSlpTSel[2] RstSlpTSel[1] RstSlpTSel[0] SCR timing 00 0 1x 00 1 2x 01 0 4x 01 1 8x 1 0 0 16x 1 0 1 32x 1 1 0 64x 1 1 1 128x |
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