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EM6682WP27 Datasheet(PDF) 2 Page - EM Microelectronic - MARIN SA |
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EM6682WP27 Datasheet(HTML) 2 Page - EM Microelectronic - MARIN SA |
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2 / 61 page  R EM6682 Copyright © 2005, EM Microelectronic-Marin SA 2 www.emmicroelectronic.com EM6682 at a glance Power Supply - Low voltage low power architecture including internal voltage regulator - 1.4 V to 5.5 V in medium voltage version - 0.9 V to 1.8 V in low voltage version - 4.0 µA in active mode - 3.5 µA in standby mode - 0.35 µA in sleep mode @ 1.5V, 32kHz, 25°C RAM - 80 x 4 bit, directly addressable ROM - 1536 x 16 bit (~3k Byte), metal mask programmable CPU - 4-bit RISC architecture - 2 clock cycles per instruction (CPI=2) - 72 basic instructions Main Operating Modes and Resets - Active mode (CPU is running) - Standby mode (CPU in halt, peripherals running) - Sleep mode (no clock, reset state, data kept) - Initial Power-On-Reset with Power-Check - power-check after any reset settable by metal option - Watchdog reset (logic) - Reset terminal (software option on PA[3/4]) - Sleep Counter reset from Sleep mode - Wakeup on change from Sleep mode Prescaler - Divider (4 stages) to best fit CPU clock (32kHz – 1MHz to 32kHz system clock to keep peripherals timing close to specification - 15 stage system clock divider from 32kHz down to 1Hz - 2 Interrupt requests (3 different frequencies) - Prescaler reset (4kHz to 1Hz) 8-Bit Serial Interface - 3 wire (Clock, DataIn , DataOut) master/slave mode - READY output during data transfer - Maximum shift clock is equal to the main system clock - Interrupt request to the CPU after 8 bit data transfer - Supports different serial formats - pins shared with general 4 bit PA[3:0] I/O port Oscillator - RC Oscillator range: 32/50kHz to 500/800kHz (metal or register selectable from 32/50, 64/100, 128/200, 256/400 or 500/800 kHz typ. for CPU clock) - No external components are necessary - Temperature compensated - External clock source possible from PA1 4(5)-Bit I/O PA[3:0] & PA[4] / PA[5]* - Direct input read on the port terminals - 2 Debounce function available muxed on 4 inputs - 2 Interrupt request on positive or negative edge - Pull-up or pull-down or none selectable by register, except PA[4] where pullup/down is mask or register selection - 2 Test variables (software) for conditional jumps - PA[1] and PA[3/4] are inputs for the event counter - PA[3/4] Reset input (register selectable) - All outputs can be put tri-state (default) - Selectable pull-downs in input mode - CMOS or Nch. open drain outputs - Weak pull-up selectable in Nch. open drain mode 4-bit ADC & Voltage Level Det. (SVLD) - External voltage compare from PA[4] input possible (low resolution 4 bit AD converter) - Levels above Vdd min are available for SVLD - Used for Power Check after POR (level 9 or level 5 selectable by metal option) - Busy flag during measure - Interrupt generated if SVLD measurement low 10-Bit Universal Counter - 10, 8, 6 or 4 bit up/down counting - Parallel load - Event counting (PA[1] or PA[3/4]) - 8 different input clocks - Full 10 bit or limited (8, 6, 4 bit) compare function - 2 interrupt requests (on compare and on 0) - Hi-frequency input on PA[1] and PA[3/4] - Pulse width modulation (PWM) output - Metal option for bit0 don’t care, reduces timer by 1 bit Interrupt Controller - 2 external and 6 internal interrupt request sources - Each interrupt request can individually be masked - Each interrupt flag can individually be reset - Automatic reset of each interrupt request after read - General interrupt request to CPU can be disabled - Automatic enabling of general interrupt request flag when going into HALT mode Sleep Counter Reset (SCR) - wake up the EM6682 from sleep mode - 4 timings selectable by register - Inhibit SCR by register Package form available - TSSOP-8/14 - SO-8/14 - Die form (9 pin possible due to additional I/O pin) NB: All frequencies written in this document are related to a typical system clock of 32 kHz ! |
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Similar Description - EM6682WP27 |
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