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EM6821WW27 Datasheet(PDF) 6 Page - EM Microelectronic - MARIN SA |
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EM6821WW27 Datasheet(HTML) 6 Page - EM Microelectronic - MARIN SA |
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6 / 68 page  R EM6821 Copyright © 2005, EM Microelectronic-Marin SA 6 www.emmicroelectronic.com 2. Operating Modes The EM6821 has two low power dissipation modes, standby and sleep. Figure 4 is a transition diagram for these modes. 2.1 Active Mode The active mode is the actual CPU running mode. Instructions are read from the internal ROM and executed by the CPU. Leaving active mode via the halt instruction to go into standby mode, the Sleep bit write to go into Sleep mode or a reset from port A to go into reset mode. 2.2 Standby Mode Executing a halt instruction puts the EM6821 into standby mode. The voltage regulator, oscillator, watchdog timer, LCD, interrupts, timers and counters are operating. However, the CPU stops since the clock related to instruction execution stops. Registers, RAM and I/O pins retain their states prior to standby mode. A reset or an interrupt request if enabled cancels standby. 2.3 Sleep Mode Writing to the Sleep bit in the RegSysCntl1 register puts the EM6821 in sleep mode. The oscillator stops and most functions of the EM6821 are inactive. To be able to write to the Sleep bit, the SleepEn bit in RegSysCntl2 must first be set to "1". In sleep mode only the voltage regulator and the reset input are active. The RAM data integrity is maintained. Sleep mode may be canceled only by a high level of min 10µs at the EM6821 Reset terminal or by the selected port A input reset combination, if option InpResSleep is turned on. Due to the cold-start characteristics of the oscillator, waking up from sleep mode may take some time to guarantee stable oscillation. During sleep mode and the following start up the EM6821 is in reset state. Waking up from sleep clears the Sleep flag but not the SleepEn bit. Inspecting the SleepEn allows to determine if the EM6821 was powered up (SleepEn = "0") or woken up from sleep (SleepEn = "1"). Table 2.3.1. Internal State in Standby and Sleep Mode Function Standby Sleep Oscillator Active Stopped Oscillator Watchdog Active Stopped Instruction Execution Stopped Stopped Interrupt Functions Active Stopped Registers and Flags Retained Reset RAM Data Retained Retained Option Registers Retained Retained Timer & Counter Active Reset Logic Watchdog Active Reset I/O Port B and Serial Port Active High Impedance, Pull’s as defined in option register Input Port A Active No pull-downs and inputs deactivated except if InpResSleep = "1" LCD Active Stopped (display off) Strobe Output Active Active Buzzer Output Active High Impedance Voltage Level Detector Finishes ongoing measure, then stop Stopped Reset Pin Active Active Figure 4 Mode transition diagram Active Halt instruction Sleep bit write IRQ Standby Sleep Reset=1 Reset=0 Reset=1 Reset=1 Reset |
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