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PRELIMINARY
CY7C1360C
CY7C1362C
Document #: 38-05540 Rev. *C
Page 2 of 31
Selection Guide
250 MHz
200 MHz
166 MHz
Unit
Maximum Access Time
2.8
3.0
3.5
ns
Maximum Operating Current
250
220
180
mA
Maximum CMOS Standby Current
30
30
30
mA
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
A0, A1, A
ADDRESS
REGISTER
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q1
Q0
ADSC
BWB
BWA
CE1
DQB,DQPB
WRITE REGISTER
DQA,DQPA
WRITE REGISTER
ENABLE
REGISTER
OE
SENSE
AMPS
MEMORY
ARRAY
ADSP
2
MODE
CE2
CE3
GW
BWE
PIPELINED
ENABLE
DQs
DQPA
DQPB
OUTPUT
REGISTERS
INPUT
REGISTERS
E
DQA,DQPA
WRITE DRIVER
OUTPUT
BUFFERS
DQB,DQPB
WRITE DRIVER
A[1:0]
ZZ
SLEEP
CONTROL
Logic Block Diagram – CY7C1362C (512K x 18)