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74HC192 Datasheet(PDF) 11 Page - NXP Semiconductors |
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74HC192 Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 13 page December 1990 11 Philips Semiconductors Product specification Presettable synchronous BCD decade up/down counter 74HC/HCT192 AC WAVEFORMS Fig.7 Waveforms showing the clock (CPU, CPD) to output (Qn) propagation delays, the clock pulse width and the maximum clock pulse frequency. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the clock (CPU, CPD) to terminal count output (TCU, TCD) propagation delays. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the parallel load input (PL) and data (Dn) to Qn output propagation delays and PL removal time to clock input (CPU, CPD). (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. |
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Similar Description - 74HC192 |
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