CY7C451
CY7C453
CY7C454
Document #: 38-06033 Rev. *A
Page 3 of 24
Pin Definitions
Signal
Name
I/O
Description
D0 – 8
I
Data Inputs: When the FIFO is not full and ENW is active, CKW (rising edge) writes data (D0 – 8) into
the FIFO’s memory. If MR is asserted at the rising edge of CKW then data is written into the FIFO’s
programming register. D8 is ignored if the device is configured for parity generation.
Q0 – 7
O
Data Outputs: When the FIFO is not empty and ENR is active, CKR (rising edge) reads data (Q0 – 7)
out of the FIFO’s memory. If MR is active at the rising edge of CKR then data is read from the
programming register.
Q8/PG/PE
O
Function varies according to mode:
Parity disabled - same function as Q0 – 7
Parity enabled, generation - parity generation bit (PG)
Parity enabled, check - Parity Error Flag (PE)
ENW
I
Enable Write: enables the CKW input (for both non-program and program modes)
ENR
I
Enable Read: enables the CKR input (for both non-program and program modes)
CKW
I
Write Clock: the rising edge clocks data into the FIFO when ENW is LOW; updates Half Full, Almost
Full, and Full flag states. When MR is asserted, CKW writes data into the program register.
CKR
I
Read Clock: the rising edge clocks data out of the FIFO when ENR is LOW; updates the Empty and
Almost Empty flag states. When MR is asserted, CKR reads data out of the program register.
HF
O
Half Full Flag - synchronized to CKW.
E/F
O
Empty or Full Flag - E is synchronized to CKR; F is synchronized to CKW
PAFE/XO
O
Dual-Mode Pin:
Not Cascaded - Programmable Almost Full is synchronized to CKW; Programmable Almost Empty is
synchronized to CKR
Cascaded - Expansion Out signal, connected to XI of next device
XI
I
Not Cascaded - XI is tied to VSS
Cascaded - Expansion Input, connected to XO of previous device
FL/RT
I
First Load/ Retransmit Pin:
Cascaded - the first device in the daisy chain will have FL tied to VSS; all other devices will have FL
tied to VCC (Figure 2)
Not Cascaded - tied to VCC;
Retransmit function is also available in stand alone mode by strobing RT
MR
I
Master Reset: resets device to empty condition.
Non-Programming Mode: program register is reset to default condition of no parity and PAFE active at
16 or less locations from Full/Empty.
Programming Mode: Data present on D0 – 8 is written into the programmable register on the rising
edge of CKW. Program register contents appear on Q0 – 8 after the rising edge of CKR.
OE
I
Output Enable for Q0 – 7 and Q8/PG/PE pins
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