the switch state. If the switch state is off, all FETs are

turned off and both NO_ (or NC_) and COM_ are high

impedance.

Negative Fault Condition

When the signal on NO_ (or NC_) and COM_ exceeds

V- by about 50mV, the low-fault comparator output is

high, turning off FETs N1 and P1. This makes the NO_

(or NC_) and COM_ pins high impedance regardless of

the switch state. If the switch state is off, all FETs are

turned off and both NO_ (or NC_) and COM_ are high

impedance.

Transient Fault Response and Recovery

When a fast rise-time and fall-time transient on NO_,

NC_, or COM_ exceeds V+ or V-, the output follows the

input to the supply rail with only a few nanoseconds

delay. This delay is due to the switch on-resistance and

circuit capacitance to ground. When the input transient

returns to within the supply rails, however, there is a

longer output recovery time delay. For positive faults,

the recovery time is typically 1µs. For negative faults,

the recovery time is typically 0.5µs. These values

depend on the output resistance and capacitance, and

are not production tested or guaranteed. The delays

are not dependent on the fault amplitude. Higher load

resistance and capacitance increase recovery times.

Fault-Protection Voltage and Power Off

The maximum fault voltage on the NO_ (or NC_) and

COM_ pins is ±36V with power applied and ±40V with

power off.

Failure Modes

Exceeding the fault-protection voltage limits on NO_,

NC_, or COM_, even for very short periods, can cause

the device to fail. See the Absolute Maximum Ratings.

The failure modes may not be obvious, and failure in

one switch may or may not affect other switches in the

same package.

Ground

There is no galvanic connection between the analog

signal paths and GND. The analog signal paths consist

of an N-channel and P-channel MOSFET with their

sources and drains paralleled and their gates driven

out of phase to V+ and V- by the logic-level translators.

However, the potential of the analog signals must be

defined or at least limited with respect to GND.

V+ and GND power the internal logic and logic-level

translators and set the input logic thresholds. The logic-

level translators convert the logic levels to switched V+

and V- signals to drive the gates of the analog switch-

es. This drive signal is the only connection between the

power supplies and the analog signals.

IN_ Logic-Level Thresholds

The logic-level thresholds are CMOS and TTL compati-

ble when V+ is +15V. As V+ is raised, the threshold

increases slightly, and when V+ reaches 25V, the level

threshold is about 2.3V, above the TTL output high-level

minimum of 2.4V, but still compatible with CMOS out-

puts (see the Typical Operating Characteristics). V- has

no effect on the logic-level thresholds.

Bipolar Supplies

The DG411F/DG412F/DG413F operate with bipolar

supplies between ±4.5V and ±20V. The V+ and V- sup-

plies need not be symmetrical, but their difference can-

not exceed the absolute maximum rating of 44V.

Single Supply

The DG411F/DG412F/DG413F operate from a single

supply between +9V and +36V when V- is connected to

GND.

Chip Information

TRANSISTOR COUNT: 251

PROCESS: CMOS

SUBSTRATE CONNECTED TO: V+

Quad, Rail-to-Rail, Fault-Protected,

SPST Analog Switches

10

______________________________________________________________________________________

Ordering Information (continued)

PART

TEMP RANGE

PIN-PACKAGE

DG412FEUE

-40°C to +85°C

16 TSSOP

DG412FDY

-40°C to +85°C

16 SO

DG412FDJ

-40°C to +85°C

16 Plastic DIP

DG413FEUE

-40°C to +85°C

16 TSSOP

DG413FDY

-40°C to +85°C

16 SO

DG413FDJ

-40°C to +85°C

16 Plastic DIP