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74HCT40105N Datasheet(PDF) 11 Page - NXP Semiconductors |
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74HCT40105N Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 25 page 1998 Jan 23 11 Philips Semiconductors Product specification 4-bit x 16-word FIFO register 74HC/HCT40105 AC WAVEFORMS Shifting in sequence FIFO empty to FIFO full Fig.6 Waveforms showing the SI input to DIR output propagation delay. The SI pulse width and SI maximum pulse frequency. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Notes to Fig.6 1. DIR initially HIGH; FIFO is prepared for valid data. 2. SI set HIGH; data loaded into input stage. 3. DIR drops LOW, input stage “busy”. 4. DIR goes HIGH, status flag indicates FIFO prepared for additional data; data from first location “ripple through”. 5. SI set LOW; necessary to complete shift-in process. 6. Repeat process to load 2nd word through to 16th word into FIFO. 7. DIR remains LOW: with attempt to shift into full FIFO, no data transfer occurs. With FIFO full; SI held HIGH in anticipation of empty location Fig.7 Waveforms showing bubble-up delay, SO input to DIR output and DIR output pulse width. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Notes to Fig.7 1. FIFO is initially, shift-in is held HIGH. 2. SO pulse; data in the output stage is unloaded, “bubble-up process of empty locations begins”. 3. DIR HIGH; when empty location reached input stage, flag indicates FIFO is prepared for data input. 4. DIR returns to LOW; FIFO is full again. 5. SI brought LOW; necessary to complete whidt-in process, DIR remains LOW, because FIFO is full. |
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