MU9C1480A/L Draft
Rev. 3.0 Draft
10
OPERATIONAL CHARACTERISTICS
Continued
Notes:
1.
Default Command Write cycle destination (does not require a TCO instruction).
2.
Default Command Write cycle destination (no TCO instruction required) if Address Field flag was set in bit 11 of the
instruction loaded in the previous cycle.
3.
Loaded or read on the Command Write or Read cycle immediately following a TCO instruction. Active for one Command
Write or Read cycle only. NFA register cannot be loaded this way.
4.
Default Command Read cycle source (does not require a TCO instruction).
5.
Default Command Read cycle source (does not require a TCO instruction) if the previous cycle was a Command Read of
Status Register Bits 15–0. If next cycle is not a Command Read cycle, any subsequent Command Read cycle will access the
Status Register Bits 15–0.
6.
Default persistent source and destination on power-up and after Reset. If other resources were sources or destinations,
SPD CR or SPS CR restores the Comparand register as the destination or source.
7.
Selected by executing a Select Persistent Destination instruction.
8.
Selected by executing a Select Persistent Source instruction.
9.
Access may require multiple 16-bit Read or Write cycles. The Segment Control register is used to control the selection of the
desired 16-bit segment(s) by establishing the Segment counters’ start and end limits and count values.
10. Device is deselected if Device Select register setting does not equal Page Address register setting, unless the Device Select
Register is set to FFFFH, which allows only write access to the device. (Writes to the Device Select register are always
active.) Device may also be deselected under locked daisy chain conditions as shown in Tables 5a and 5b on page 12.
11. A Command Read cycle after a TCO PS or TCO PD reads back the Instruction decoder bits that were last set to select a
persistent source or destination. The TCO PS instruction will also read back the Device ID.
/CM
L
L
H
H
X
/W
L
H
L
H
X
I/O Status
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
HIGH-Z
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
HIGH-Z
HIGH-Z
Operation
Load Instruction decoder
Load Address register
Load Control register
Load Page Address register
Load Segment Control register
Load Device Select register
Deselected
Read Next Free Address register
Read Address register
Read Status Register bits 15–0
Read Status Register bits 31–16
Read Control register
Read Page Address register
Read Segment Control register
Read Device Select register
Read Current Persistent Source or Destination
Deselected
Load Comparand register
Load Mask Register 1
Load Mask Register 2
Write Memory Array at address
Write Memory Array at Next Free address
Write Memory Array at Highest-Priority match
Deselected
Read Comparand register
Read Mask Register 1
Read Mask Register 2
Read Memory Array at address
Read Memory Array at Highest-Priority match
Deselected
Deselected
Cycle Type
Cmd Write
Cmd Read
Data Write
Data Read
/E
L
L
L
L
H
Notes
1
2,3
3
3
3
3
10
3
3
4
5
3
3
3
3
3,11
10
6,9
7,9
7,9
7,9
7,9
7,9
10
6, 9
8, 9
8, 9
8, 9
7, 8
10
SPS
ü
ü
ü
ü
ü
SPD
ü
ü
ü
ü
ü
ü
TCO
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
Table 3: Input/Output Operations
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