X40430/X40431 – Preliminary Information

Characteristics subject to change without notice.

2 of 24

REV 1.2.3 11/28/00

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A manual reset input provides debounce circuitry for

minimum reset component count.

The Watchdog Timer provides an independent protec-

tion mechanism for microcontrollers. When the micro-

controller fails to restart a timer within a selectable time

out interval, the device activates the WDO signal. The

user selects the interval from three preset values. Once

selected, the interval does not change, even after

cycling the power.

The memory portion of the device is a CMOS Serial

EEPROM array with Xicor’s Block Lock protection. The

array is internally organized as x 8. The device features

a 2-wire interface and software protocol allowing opera-

cell, providing a minimum endurance of 1,000,000

cycles and a minimum data retention of 100 years.

PIN CONFIGURATION

PIN DESCRIPTION

Pin

Name

Function

1

V2FAIL

2

V2MON

LOW. This input can monitor an unregulated power supply with an external resistor divider or can

when not used.

3

LOWLINE

when

4NC

No connect.

5MR

Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will

6

RESET/

RESET

RESET Output. (X40431) This open drain pin is an active LOW output which goes LOW whenever

RESET Output. (X40430) This pin is an active HIGH CMOS output which goes HIGH whenever

Ground

V3MON

SDA

SCL

3

2

4

1

12

13

11

14

LOWLINE

NC

RESET

7

6

5

8

9

10

V2MON

MR

WP

3

2

4

1

12

13

11

14

7

6

5

8

9

10

V3FAIL

WDO

V2FAIL

V3MON

SDA

SCL

WP

V3FAIL

WDO

LOWLINE

NC

RESET

V2MON

MR

V2FAIL

X40430

X40431

14-Pin SOIC, TSSOP

14-Pin SOIC, TSSOP