December 1990

2

Philips Semiconductors

Product specification

8-bit shift register with input flip-flops

74HC/HCT597

FEATURES

• 8-bit parallel storage register inputs

• Shift register has direct overriding load and clear

• Output capability: standard

GENERAL DESCRIPTION

The 74HC/HCT597 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT597 consist each of an 8-bit storage

register feeding a parallel-in, serial-out 8-bit shift register.

Both the storage register and the shift register have

positive edge-triggered clocks. The shift register also has

direct load (from storage) and clear inputs.

QUICK REFERENCE DATA

Notes

ORDERING INFORMATION

See

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HC

HCT

propagation delay

17

20

ns

25

29

ns

PL to Q

21

26

ns

96

83

MHz

input capacitance

3.5

3.5

pF

power dissipation capacitance per package

notes 1 and 2

29

32

pF