RTL8201CP
Datasheet
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
iii
Track ID: JATR-1076-21 Rev. 1.21
Table of Contents
1.
GENERAL DESCRIPTION................................................................................................................................................1
2.
FEATURES...........................................................................................................................................................................1
3.
BLOCK DIAGRAM.............................................................................................................................................................2
4.
PIN ASSIGNMENTS ...........................................................................................................................................................3
5.
PIN DESCRIPTION ............................................................................................................................................................4
5.1.
MII INTERFACE............................................................................................................................................................4
5.2.
SNI (SERIAL NETWORK INTERFACE) 10MBPS ONLY....................................................................................................5
5.3.
CLOCK INTERFACE .......................................................................................................................................................5
5.4.
10MBPS/100MBPS NETWORK INTERFACE....................................................................................................................5
5.5.
DEVICE CONFIGURATION INTERFACE ...........................................................................................................................6
5.6.
LED INTERFACE/PHY ADDRESS CONFIGURATION.......................................................................................................6
5.7.
POWER AND GROUND PINS ..........................................................................................................................................7
5.8.
RESET AND OTHER PINS...............................................................................................................................................7
6.
REGISTER DESCRIPTIONS ............................................................................................................................................8
6.1.
REGISTER 0 BASIC MODE CONTROL REGISTER............................................................................................................8
6.2.
REGISTER 1 BASIC MODE STATUS REGISTER ...............................................................................................................9
6.3.
REGISTER 2 PHY IDENTIFIER REGISTER 1 ...................................................................................................................9
6.4.
REGISTER 3 PHY IDENTIFIER REGISTER 2 ...................................................................................................................9
6.5.
REGISTER 4 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (ANAR) ....................................................................10
6.6.
REGISTER 5 AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (ANLPAR)......................................................10
6.7.
REGISTER 6 AUTO-NEGOTIATION EXPANSION REGISTER (ANER) .............................................................................11
6.8.
REGISTER 16 NWAY SETUP REGISTER (NSR) ............................................................................................................12
6.9.
REGISTER 17 LOOPBACK, BYPASS, RECEIVER ERROR MASK REGISTER (LBREMR) ................................................12
6.10.
REGISTER 18 RX_ER COUNTER (REC).....................................................................................................................13
6.11.
REGISTER 19 SNR DISPLAY REGISTER ......................................................................................................................13
6.12.
REGISTER 25 TEST REGISTER.....................................................................................................................................13
7.
FUNCTIONAL DESCRIPTION.......................................................................................................................................14
7.1.
MII AND MANAGEMENT INTERFACE ..........................................................................................................................14
7.1.1.
Data Transition.....................................................................................................................................................14
7.1.2.
Serial Management...............................................................................................................................................15
7.2.
AUTO-NEGOTIATION AND PARALLEL DETECTION ......................................................................................................16
7.2.1.
Setting the Medium Type and Interface Mode to MAC.........................................................................................16
7.2.2.
UTP Mode and MII Interface ...............................................................................................................................16
7.2.3.
UTP Mode and SNI Interface ...............................................................................................................................17
7.2.4.
Fiber Mode and MII Interface..............................................................................................................................17
7.3.
FLOW CONTROL SUPPORT ..........................................................................................................................................17
7.4.
HARDWARE CONFIGURATION AND AUTO-NEGOTIATION ............................................................................................18
7.5.
LED AND PHY ADDRESS CONFIGURATION................................................................................................................19
7.6.
SERIAL NETWORK INTERFACE....................................................................................................................................20
7.7.
POWER DOWN, LINK DOWN, POWER SAVING, AND ISOLATION MODES......................................................................20
7.8.
MEDIA INTERFACE .....................................................................................................................................................20
7.8.1.
100Base-TX ..........................................................................................................................................................20
7.8.2.
100Base-FX Fiber Mode Operation.....................................................................................................................21
7.8.3.
10Base-T TX/RX ...................................................................................................................................................21
7.9.
REPEATER MODE OPERATION.....................................................................................................................................22
7.10.
RESET, AND TRANSMIT BIAS ......................................................................................................................................22
7.11.
3.3V POWER SUPPLY AND VOLTAGE CONVERSION CIRCUIT.......................................................................................22
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