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ATR2434 Datasheet(PDF) 8 Page - ATMEL Corporation |
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ATR2434 Datasheet(HTML) 8 Page - ATMEL Corporation |
8 / 35 page 8 ATR2434 [Preliminary] 4822C–ISM–09/04 Figure 6. SPI Burst Write Sequence DIO Interface The DIO communications interface is an optional SERDES bypass data-only transfer interface. In receive mode, DIO and DIOVAL are valid after the falling edge of IRQ, which clocks the data as shown in Figure 7. In transmit mode, DIO and DIOVAL are sampled on the falling edge of the IRQ, which clocks the data as shown in Figure 8. The application MCU samples the DIO and DIOVAL on the rising edge of IRQ. Figure 7. DIO Receive Sequence Figure 8. DIO Transmit Sequence SS MO S I MIS O SC K A0 A1 A2 A3 A4 A5 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 data from m cu 1 data from m cu 1+N addr cm d DIR INC 11 DIOVAL DIO IRQ d7 d6 d5 d4 d3 d2 d... d14 d13 d12 d11 d10 d9 d8 d1 d0 data to mcu v7 v6 v5 v4 v3 v2 v... v14 v13 v12 v11 v10 v9 v8 v1 v0 DIOVAL DIO IRQ d7 d6 d5 d4 d3 d2 d... d14 d13 d12 d11 d10 d9 d8 d1 d0 data from mcu v7 v6 v5 v4 v3 v2 v... v14 v13 v12 v11 v10 v9 v8 v1 v0 |
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