DDU8C

Doc #97013

DATA DELAY DEVICES, INC.

1

1/28/97

3 Mt. Prospect Ave. Clifton, NJ 07013

5-TAP, HCMOS-INTERFACED

FIXED DELAY LINE

(SERIES DDU8C)

FEATURES

PACKAGES

•

Five equally spaced outputs

•

Fits standard 8-pin DIP socket

•

Low profile

•

Auto-insertable

•

Input & outputs fully CMOS interfaced & buffered

•

10 T

FUNCTIONAL DESCRIPTION

The DDU8C-series device is a 5-tap digitally buffered delay line. The

signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an

amount determined by the device dash number (See Table). The total

delay of the line is measured from IN to T5. The nominal tap-to-tap delay

increment is given by one-fifth of the total delay.

SERIES SPECIFICATIONS

•

Minimum input pulse width: 40% of total delay

•

Output rise time: 8ns typical

•

Supply voltage:

5VDC

± 5%

•

Supply current:

µa typical

•

Operating temperature: 0

° to 70° C

•

Temp. coefficient of total delay: 300 PPM/

°C

20%

20%

20%

20%

20%

VDD

GND

IN

T1

T2

T3

T4

T5

DDU8C Functional diagram

©

©1997 Data Delay Devices

data

delay

®

®

3

1

2

3

4

5

6

7

14

13

12

11

10

9

8

IN

N/C

N/C

T2

N/C

T4

GND

VDD

N/C

T1

N/C

T3

N/C

T5

8

7

6

5

1

2

3

4

IN

T2

T4

GND

VDD

T1

T3

T5

DDU8C-xx

DIP

DDU8C-xxA1 Gull-Wing

DDU8C-xxB1 J-Lead

DDU8C-xxM Military DIP

Military SMD

DDU8C-xxMD1

DDU8C-xxMD4

PIN DESCRIPTIONS

IN

Signal Input

T1-T5 Tap Outputs

VDD

+5 Volts

GND

Ground

DASH NUMBER SPECIFICATIONS

Part

Number

Total

Delay (ns)

Delay Per

Tap (ns)

DDU8C-5050

50

± 2.5

10.0

± 3.0

DDU8C-5060

60

± 3.0

12.0

± 3.0

DDU8C-5075

75

± 4.0

15.0

± 3.0

DDU8C-5100

100

± 5.0

20.0

± 3.0

DDU8C-5125

125

± 6.5

25.0

± 3.0

DDU8C-5150

150

± 7.5

30.0

± 3.0

DDU8C-5175

175

± 8.0

35.0

± 4.0

DDU8C-5200

200

± 10.0

40.0

± 4.0

DDU8C-5250

250

± 12.5

50.0

± 5.0

NOTE: Any dash number between 5004 and 5250

not shown is also available.