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IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO

DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8

INDUSTRIALTEMPERATURERANGE

PIN DESCRIPTIONS

The IDT72V10071/72V11071/72V12071/72V13071/72V14071's two

FIFOs, referred to as FIFO A and FIFO B, are identical in every respect.

FIFO A and FIFO B operate completely independent from each other.

Symbol

Name

I/O

Description

DA0-DA7

A Data Inputs

I

8-bit data inputs to FIFO array A.

DB0-DB7

B Data Inputs

I

8-bit data inputs to FIFO array B.

RSA, RSB

Reset

I

When

RSA(RSB) is set LOW, the associated internal read and write pointers of array A (B) are set to the first

location;

FFA (FFB) go as HIGH and EFA (EFB) go as LOW. After power-up, a reset of both FIFOs A and B

is required before an initial WRITE.

WCLKA

Write Clock

I

Data is written into the FIFO A (B) on a LOW-to-HIGH transition of WCLKA (WCLKB) when the write enable

WCLKB

is asserted.

WENA

Write Enable

I

When

WENA (WENB) is LOW, data A (B) is written into the FIFO on every LOW-to-HIGH transition WCLKA

WENB

(WCLKB). Data will not be written into the FIFO if

FFA (FFB) is LOW.

QA0-QA7

A Data Outputs

O 8-bit data outputs from FIFO array A.

QB0-QB7

B Data Outputs

O 8-bit data outputs from FIFO array B.

RCLKA

Read Clock

I

Data is read from FIFO A (B) on a LOW-to-HIGH transition of RCLKA (RCLKB) when

RENA (RENB) is

RCLKB

asserted.

RENA

Read Enable

I

When

RENA (RENB) is LOW, data is read from FIFO A (B) on every LOW-to-HIGH transition of RCLKA

RENB

(RCLKB). Data will not be read from Array A (B) if

EFA (EFB) is LOW.

OEA

Output Enable

I

When

OEA(OEB) is LOW, outputs DA0-DA7 (DB0-DB7) are active. If OEA(OEB) is HIGH, outputs

OEB

DA0-DA7 (DB0-DB7) will be in a high-impedance state.

EFA

Empty Flag

O When

EFA (EFB) is LOW, FIFO A (B) is empty and further data reads from the output are inhibited. When

EFB

EFA (EFB) is HIGH, FIFO A (B) is not empty. EFA (EFB) is synchronized to RCLKA (RCLKB).

FFA

Full Flag

O When

FFA (FFB) is LOW, FIFO A (B) is full and further data writes into the input are inhibited. When FFA

FFB

(

FFB) is HIGH, FIFO A (B) is not full. FFA (FFB) is synchronized to WCLKA (WCLKB).

Power

+3.3V power supply pin.

GND

Ground

0V ground pin.