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MITSUBISHI ELECTRIC

Jun,'00

Preliminary

MITSUBISHI LSIs

DDR SDRAM (Rev.0.1)

M2S28D20/ 30/ 40ATP

128M Double Data Rate Synchronous DRAM

PRELIMINARY

Some of contents are subject to change without notice.

DESCRIPTION

M2S28D20ATP is a 4-bank x 8388608-word x 4-bit,

M2S28D30ATP is a 4-bank x 4194304-word x 8-bit,

M2S28D40ATP is a 4-bank x 2097152-word x 16-bit,

double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are

referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output

data and data strobe are referenced on both edges of CLK. The M2S28D20/30/40ATP achieves very

high speed data rate up to 133MHz, and are suitable for main memory in computer systems.

FEATURES

- Vdd=Vddq=2.5V+0.2V

- Double data rate architecture;

two data transfers per clock cycle

- Bidirectional, data strobe (DQS) is transmitted/received with data

- Differential clock inputs (CLK and /CLK)

- DLL aligns DQ and DQS transitions

with CLK transitions edges of DQS

- Commands entered on each positive CLK edge;

- data and data mask referenced to both edges of DQS

- 4 bank operation controlled by BA0, BA1 (Bank Address)

- /CAS latency- 2.0/2.5 (programmable)

- Burst length- 2/4/8 (programmable)

- Burst type- sequential / interleave (programmable)

- Auto precharge / All bank precharge controlled by A10

- 4096 refresh cycles /64ms (4 banks concurrent refresh)

- Auto refresh and Self refresh

- Row address A0-11 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)

- SSTL_2 Interface

- 400-mil, 66-pin Thin Small Outline Package (TSOP II)

- FET switch control(/QFC) for x4/ x8

- JEDEC standard