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M2V28S30ATP-7 Datasheet(PDF) 4 Page - Mitsubishi Electric Semiconductor |
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M2V28S30ATP-7 Datasheet(HTML) 4 Page - Mitsubishi Electric Semiconductor |
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4 / 51 page  M2V28S20ATP -6,-6L,-7,-7L,-8,-8L M2V28S30ATP -6,-6L,-7,-7L,-8,-8L M2V28S40ATP -6,-6L,-7,-7L,-8,-8L Nov. '99 MITSUBISHI LSIs SDRAM (Rev. 1.0E) 128M Synchronous DRAM (4-BANK x 8,388,608-WORD x 4-BIT) (4-BANK x 4,194,304-WORD x 8-BIT) (4-BANK x 2,097,152-WORD x 16-BIT) MITSUBISHI ELECTRIC 4 PIN FUNCTION CLK Input Master Clock: All other inputs are referenced to the rising edge of CLK. CKE Input Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / selfrefresh. After self refresh mode is started, CKE becomes synchronous input. Self refresh is maintained as long as CKE is low. /CS Input Chip Select: When /CS is high, any command means No Operation. /RAS, /CAS, /WE Input Combination of /RAS, /CAS, /WE defines basic commands. A0-11 Input A0-11 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-11. The Column Address is specified by A0-9,11 (x4) / A0-9 (x8) / A0-8 (x16). A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. BA0,1 Input Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands. DQ0-7 Input / Output DQM Input Din Mask / Output Disable: When DQM is high in burst write, Din for the current cycle is masked. When DQM is high in burst read, Dout is disabled at the next but one cycle. Vdd, Vss Power Supply Power Supply for the memory array and peripheral circuitry. VddQ, VssQ Power Supply VddQ and VssQ are supplied to the Output Buffers only. Data In and Data out are referenced to the rising edge of CLK. |
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