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M5M4V4265CTP-7S Datasheet(PDF) 6 Page - Mitsubishi Electric Semiconductor |
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M5M4V4265CTP-7S Datasheet(HTML) 6 Page - Mitsubishi Electric Semiconductor |
6 / 31 page EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs M5M4V4265CJ,TP-5,-5S:under development 6 Read-Write and Read-Modify-Write Cycles Limits Parameter Read write/read modify write cycle time RAS low pulse width CAS low pulse width Symbol tRWC Unit Min Max Min Max ns ns ns ns ns ns tRAS tCAS tCSH tRSH tRCS CAS hold time after RAS low RAS hold time after CAS low Read setup time before CAS low (Note 23) (Note 24) ns ns ns tCWD tRWD tAWD Delay time, CAS low to W low Delay time, RAS low to W low Delay time, address to W low OE hold time after W low tOEH 15 20 ns 10000 10000 10000 10000 44 89 44 82 0 32 77 47 133 Note 23 : tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT. Note 24 : tWCS, tCWD, tRWD and tAWD and tCPWD are specified as reference points only. If tWCS ≥tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD ≥tCWD(min), tRWD≥tRWD(min), tAWD≥tAWD(min) and tCPWD≥tCPWD(min) (for EDO mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes back to VIH) is indeterminate. 57 107 57 99 0 42 92 57 161 (Note 24) (Note 24) M5M4V4265C-6,-6S M5M4V4265C-7,-7S Write Cycle (Early Write and Delayed Write) Limits Parameter Write cycle time RAS low pulse width CAS low pulse width Symbol tWC Unit Min Max Min Max ns ns ns ns ns ns tRAS tCAS tCSH tRSH tWCS CAS hold time after RAS low Write setup time before CAS low Write hold time after CAS low (Note 24) tWCH tCWL ns ns tRWL tWP tDS RAS hold time after CAS low CAS hold time after W low ns ns ns 10000 10000 10000 10000 ns 10 0 110 60 10 48 15 10 10 10 0 10 tDH RAS hold time after W low Data setup time before CAS low or W low Data hold time after CAS low or W low Write pulse width 13 0 130 70 10 55 20 13 13 0 13 13 M5M4V4265C-6,-6S M5M4V4265C-7,-7S Min Max 10000 10000 8 0 90 50 8 40 13 8 8 8 0 8 M5M4V4265C-5,-5S Min Max 13 10000 10000 38 75 38 70 0 28 65 40 109 M5M4V4265C-5,-5S |
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