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M5M4V4405CTP-6S Datasheet(PDF) 9 Page - Mitsubishi Electric Semiconductor |
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M5M4V4405CTP-6S Datasheet(HTML) 9 Page - Mitsubishi Electric Semiconductor |
9 / 27 page EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM M5M4V4405CJ,TP-6,-7,-6S,-7S MITSUBISHI LSIs Parameter Symbol Limits Unit Min Max Min Max 9 tWHR tWSR Test Mode Set Cycle 10 10 10 15 M5M4V4405C-6,-6S M5M4V4405C-7,-7S ns ns Hyper page Mode Cycle (Read, Early Write, Read-Write, Read-Modify-Write Cycle, Read Write Mix Cycle, Hi-Z control by M5M4V4405C-6,-6S M5M4V4405C-7,-7S ns ns ns ns ns (Note 26) (Note 27) tHPC tHPRWC tRAS tCPRH tCPWD ns ns ns ns ns ns (Note 24) tHCWD tHAWD tHPWD tHCOD tHAOD tHPOD 38 30 82 55 100000 71 43 35 97 65 100000 84 37 47 52 62 55 65 20 25 35 40 38 43 Parameter Symbol Limits Unit Min Max Min Max Hyper page mode read/write cycle time RAS low pulse width for read or write cycle RAS hold time after CAS precharge Delay time, CAS precharge to W low Hyper Page Mode read write / read modify write cycle time Delay time, CAS low to W low after read Delay time, Address to W low after read Delay time, CAS precharge to W low after read Delay time, CAS low to OE high after read Delay time, Address to OE high after read Delay time, CAS precharge to OE high after read Write setup time before RAS low Write hold time after RAS low OE or W) (Note 25) |
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