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M5M44265CJ-5S Datasheet(PDF) 4 Page - Mitsubishi Electric Semiconductor |
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M5M44265CJ-5S Datasheet(HTML) 4 Page - Mitsubishi Electric Semiconductor |
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4 / 31 page  EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM M5M44265CJ,TP-5,-6,-7,-5S,-6S,-7S MITSUBISHI LSIs 4 Note 6: An initial pause of 500µs is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh cycles). Note the RAS may be cycled during the initial pause. And 8 initialization cycles are required after prolonged periods (greater than 8.2ms) of RAS inactivity before proper device operation is achieved. 7: Measured with a load circuit equivalent to 1TTL and 50pF. The reference levels for measuring of output signals are 2.0V(VOH) and 0.8V(VOL). 8: Assumes that tRCD ≥ tRCD(max) and tASC ≥ tASC(max) and tCP ≥ tCP(max). 9: Assumes that tRCD ≤ tRCD(max) and tRAD ≤ tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC will increase by amount that tRCD exceeds the value shown. 10: Assumes that tRAD ≥ tRAD(max) and tASC ≤ tASC(max). 11: Assumes that tCP ≤ tCP(max) and tASC ≥ tASC(max). 12: tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT ≤ ±10µA ) and is not reference to VOH(min) or VOL(max). 13: Output is disabled after both RAS and CAS go to high. SWITCHING CHARACTERISTICS (Ta=0~70˚C, VCC=5V±10%, VSS=0V, unless otherwise noted, see notes 6,14,15) Limits Min Max Parameter Access time from CAS Access time from RAS Columu address access time Symbol tCAC Unit Min Max Min Max ns ns ns ns ns ns 5 15 30 33 15 60 tRAC tAA tCPA tOEA tCLZ Access time from CAS precharge Output low impedance time from CAS low Output disable time after CAS high (Note 7,8) (Note 7,9) (Note 7,10) (Note 7,11) (Note 7) 5 tOFF tOEZ (Note 12) (Note 7) Output disable time after OE high Access time from OE 15 15 5 13 25 28 13 50 13 13 ns ns 20 35 38 70 20 20 20 M5M44265C-5,-5S M5M44265C-6,-6S M5M44265C-7,-7S CAPACITANCE Limits Min Max Unit Typ pF pF pF Input capacitance, address inputs CI (A) CI (CLK) CI / O Symbol Parameter Test conditions Input capacitance, clock inputs Input/Output capacitance, data ports 5 7 VI=VSS f=1MHz VI=25mVrms 7 (Ta=0~70˚C, VCC=5V±10%, VSS=0V, unless otherwise noted) Output disable time after WE high Output disable time after RAS high Output hold time from CAS Output hold time from RAS (Note 13) tOHC tOHR tWEZ tREZ (Note 13) (Note 12,13) (Note 12) 15 15 13 13 ns ns 20 20 ns 5 5 5 ns 5 5 5 (Note 12,13) |
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