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M5M29GB161BWG Datasheet(PDF) 11 Page - Mitsubishi Electric Semiconductor |
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M5M29GB161BWG Datasheet(HTML) 11 Page - Mitsubishi Electric Semiconductor |
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11 / 25 page  MITSUBISHI LSIs 16,777,216-BIT (2097,152-WORD BY 8-BIT / 1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY M5M29GB/T160BVP-80 Sep 1999. Rev2.0 11 Read-Only Mode AC ELECTRICAL CHARACTERISTICS (Ta = -40 ~85 °C) Read timing parameters during command write operations mode are the same as during read-only operations mode. Typical values at Vcc=3.3V, Ta=25 °C AC ELECTRICAL CHARACTERISTICS (Ta = -40 ~85 °C) Write Mode (WE# control) Symbol Parameter Write cycle time Data hold time Data set-up time Address hold time Address set-up time tAVAV tWHDX tDVWH tWHAX tAVWH tWC tDH tDS tAH tAS Limits 80 50 50 Max Min Typ 0 0 Unit ns ns ns ns ns 90 50 50 Max Min Typ 0 0 Write pulse width Chip enable hold time Chip enable set-up time Write pulse width high Block Lockhold from valid SRD Duration of auto-program operation Duration of auto-block erase operation Block Lock set-up to write enable high tWLWH tWHEH tELWL tWHWL tQVPH tWHRH1 tWHRH2 tPHHWH tWP tCH tCS tWPH tBLS tBLH tDAP tDAE OE# hold to WE# Low tGHWL tGHWL 4 40 80 600 60 0 30 0 80 0 0 ns ns ns ns ns ms ms ns 4 40 80 600 60 0 30 0 90 0 ns 0 Symbol Parameter ta (AD) Address access time tAVQV tCLZ Chip enable to output in low-Z tELQX ta (CE) Chip enable access time tELQV ta (OE) Output enable access time tGLQV tDF(CE) Chip enable high to output in high Z tEHQZ tRC Read cycle time tAVAV tOLZ tGLQX Output enable to output in low-Z tDF(OE) tGHQZ Output enable high to output in high Z tPHZ RP# low to output high-Z tPLQZ Unit ns ns ns ns ns ns ns ns ns 80 0 80 30 25 80 0 25 150 Max Min Typ 90 0 90 30 25 90 0 25 150 Max Min Typ Limits Speed Item: -80 Vcc=2.7~3.6V Vcc=3.3V+/-0.3V Speed Item: -80 Vcc=2.7~3.6V Vcc=3.3V+/-0.3V ns ns 10 10 30 30 OE# hold from WE# high tWHGL tOEH Latency between Read and Write FFH or 71H - tRE Timing measurements are made under AC waveforms for read operations. tWHGL OE# hold from WE# high tOEH tBAD tAVFL/H RP# recovery to CE# low ns ns ns tPS tPHEL 10 0 150 10 0 150 tELFL/H F-CE# low to BYTE# high or low tBCD tOH Output hold from CE#, OE#, addresses tOH Address to BYTE# high or low 5 5 5 5 ta(BYTE) BYTE# access time tFL/HQV tBHZ BYTE# low to output high-Z tFLQZ 80 25 90 25 Byte enable high or low set-up time tFL/HWH tBS tWHFL/H tBH Byte enable high or low hold time 50 80 50 90 ns ns ns ns ns ns 0 RP# high recovery to write enable low tPHWL tPS 150 ns 150 Write enable high to F-RY/BY# low tWHRL tWHRL 90 ns 90 |
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