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HAL300 Datasheet(PDF) 11 Page - Micronas |
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HAL300 Datasheet(HTML) 11 Page - Micronas |
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11 / 17 page  HAL300 11 Micronas 20 22 24 26 28 30 µA VOH IOH V 10 0 10 –1 10 –2 10 –3 10 –4 10 –5 10 1 10 2 VDD = 5 V TA = 125 °C TA = 75 °C TA = 25 °C Fig. 20: Typical output leakage current versus output voltage Application Notes Mechanical stress can change the sensitivity of the Hall plates and an offset of the magnetic switching points may result. External mechanical stress to the package can influence the magnetic parameters if the sensor is used under back-biased applications. This piezo sensi- tivity of the sensor IC cannot be completely compen- sated for by the switching offset compensation tech- nique. For back-biased applications, the HAL 320 is recom- mended. In such cases, please contact our Application Department. They will provide assistance in avoiding applications which may induce stress to the ICs. This stress may cause drifts of the magnetic parameters indi- cated in this data sheet. For electromagnetic immunity, it is recommended to ap- ply a 4.7 nF capacitor between VDD (pin 1) and Ground (pin 2). For automotive applications, a 220 W series re- sistor to pin 1 is recommended. Because of the IDD peak at 4.1 V, the series resistor should not be greater than 270 Ω. The series resistor and the capacitor should be placed as close as possible to the IC. Ambient Temperature Due to the internal power dissipation, the temperature on the silicon chip (junction temperature TJ) is higher than the temperature outside the package (ambient tem- perature TA). TJ = TA + ∆T At static conditions, the following equations are valid: – for SOT-89A: ∆T = IDD * VDD * RthJSB – for TO-92UA: ∆T = IDD * VDD * RthJA For typical values, use the typical parameters. For worst case calculation, use the max. parameters for IDD and Rth, and the max. value for VDD from the application. Test Circuits for Electromagnetic Compatibility Test pulses VEMC corresponding to DIN 40839. OUT GND 3 2 1VDD 4.7 nF VEMC VP RV 220 Ω RL 1.2 k Ω 20 pF Fig. 21: Test circuit 2: test procedure for class A OUT GND 3 2 1VDD 4.7 nF VEMC RV 220 Ω RL 680 Ω Fig. 22: Test circuit 1: test procedure for class C |
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