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M5M417400CJ Datasheet(PDF) 8 Page - Mitsubishi Electric Semiconductor |
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M5M417400CJ Datasheet(HTML) 8 Page - Mitsubishi Electric Semiconductor |
8 / 22 page MITSUBISHI LSIs M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM 8 TIMING REQUIREMENTS (Ta = 0 ~ 70°C, VCC = 5V ± 10%, VSS = 0V, unless otherwise noted, see notes 12, 13) SELF REFRESH ENTRY & EXIT CONDITIONS 1. In case of distributed refresh The last / first full refresh cycles (2K) must be made within tNS / tSN before / after self refresh, on the condition of tNS ≤ 32ms and tSN ≤ 32ms. 2. In case of burst refresh The last / first full refresh cycles (2K) must be made within tNS / tSN before / after self refresh, on the condition of tNS + tSN ≤ 32ms. Symbol Parameter Limits Unit M5M417400C-5S M5M417400C-6S M5M417400C-7S Min Max Min Max Min Max tRASS Self Refresh RAS low pulse width 100 100 100 µs tRPS Self Refresh RAS high precharge time 90 110 130 ns tCHS Self Refresh RAS hold time -50 -50 -50 ns tRSR Read setup time before RAS low 101010 ns tRHR Read hold time after RAS low 101015 ns |
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