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M5M417400CTP-5 Datasheet(PDF) 5 Page - Mitsubishi Electric Semiconductor

Part # M5M417400CTP-5
Description  FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
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Manufacturer  MITSUBISHI [Mitsubishi Electric Semiconductor]
Direct Link  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor

M5M417400CTP-5 Datasheet(HTML) 5 Page - Mitsubishi Electric Semiconductor

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MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
5
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write, Refresh, and Fast-Page Mode Cycles)
(Ta = 0 ~ 70°C, VCC = 5V ± 10%, VSS = 0V, unless otherwise noted. See notes 12, 13)
Note 12:
The timing requirements are assumed tT = 5ns.
13:
VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
14:
tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access time is controlled exclusively by
tCAC or tAA. tRCD(min) is specified as tRCD(min) = tRAH(min) + 2tH + tASC(min).
15:
tRAD(max) is specified as a reference point only. If tRAD ≥ tRAD(max) and tASC ≤ tASC(max), access time is controlled exclusively by tAA.
16:
tASC(max) is specified as a reference point only. If tRCD ≥ tRCD(max) and tASC ≥ tASC(max), access time is controlled exclusively by tCAC.
17:
Either tDZC or tDZO must be satisfied.
18:
Either tCDD or tODD must be satisfied.
19:
tT is measured between VIH(min) and VIL(max).
Read and Refresh Cycles
Note 20:
Either tRCH or tRRH must be satisfied for a read cycle.
Symbol
Parameter
Limits
Unit
M5M417400C-5,-5S
M5M417400C-6,-6S
M5M417400C-7,-7S
Min
Max
Min
Max
Min
Max
tREF
Refresh cycle time
32
32
32
ms
tRP
RAS high pulse width
30
40
50
ns
tRCD
Delay time, RAS low to CAS low
(Note 14)
183720452050
ns
tCRP
Delay time, CAS high to RAS low
101010
ns
tRPC
Delay time, RAS high to CAS low
000
ns
tCPN
CAS high pulse width
10
10
10
ns
tRAD
Column address delay time from RAS low
(Note 15)
132515301535
ns
tASR
Row address setup time before RAS low
000
ns
tASC
Column address setup time before CAS low
(Note 16)
0
10010010
ns
tRAH
Row address hold time after RAS low
8
10
10
ns
tCAH
Column address hold time after CAS low
131515
ns
tDZC
Delay time, data to CAS low
(Note 17)
0
0
0
ns
tDZO
Delay time, data to OE low
(Note 17)
0
0
0
ns
tCDD
Delay time, CAS high to data
(Note 18)
13
15
15
ns
tODD
Delay time, OE high to data
(Note 18)
13
15
15
ns
tT
Transition time
(Note 19)
1
50
1
50
1
50
ns
Symbol
Parameter
Limits
Unit
M5M417400C-5,-5S
M5M417400C-6,-6S
M5M417400C-7,-7S
MinMax
MinMax
MinMax
tRC
Read cycle time
90
110
130
ns
tRAS
RAS low pulse width
50
10000
60
10000
70
10000
ns
tCAS
CAS low pulse width
13
10000
15
10000
20
10000
ns
tCSH
CAS hold time after RAS low
506070
ns
tRSH
RAS hold time after CAS low
131520
ns
tRCS
Read setup time after CAS high
0
0
0
ns
tRCH
Read hold time after CAS low
(Note 20)
0
0
0
ns
tRRH
Read hold time after RAS low
(Note 20)
10
10
10
ns
tRAL
Column address to RAS hold time
25
30
35
ns
tOCH
CAS hold time after OE low
131520
ns
tORH
RAS hold time after OE low
131520
ns


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