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M5M467400J-6 Datasheet(PDF) 11 Page - Mitsubishi Electric Semiconductor |
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M5M467400J-6 Datasheet(HTML) 11 Page - Mitsubishi Electric Semiconductor |
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11 / 37 page  MITSUBISHI ELECTRIC Jun. 1999 FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM MITSUBISHI LSIs (Rev. 1.1) M5M467400/465400BJ,BTP -5,-6,-5S,-6S M5M467800/465800BJ,BTP -5,-6,-5S,-6S M5M465160BJ,BTP -5,-6,-5S,-6S 11 Write Cycle (Early Write and Delayed Write) Parameter Symbol Read-Write and Read-Modify-Write Cycles Limits Parameter Symbol Limits Unit Read write/read modify write cycle time RAS low pulse width CAS low pulse width tRWC tRAS tCAS tCSH tRSH tRCS CAS hold time after RAS low RAS hold time after CAS low Read setup time before CAS low (Note22) (Note23) 50 50 0 30 75 45 50 126 50 85 0 30 65 40 tCWD tRWD tAWD Delay time, CAS low to W low Delay time, RAS low to W low Delay time, address to W low (Note23) (Note23) 10000 10000 10000 10000 85 150 95 95 ns ns ns ns ns ns ns ns Min Max Min Max ns OE hold time after W low ns 15 13 tOEH Write cycle time RAS low pulse width CAS low pulse width tWC 8 tRAS tCAS tCSH tRSH tWCS CAS hold time after RAS low Write setup time before CAS low Write hold time after CAS low (Note 23) tWCH tCWL 0 tRWL tWP tDS RAS hold time after CAS low CAS hold time after W low 10000 10000 10000 10000 90 50 13 50 13 8 0 10 0 110 60 15 60 15 10 0 8 10 tDH RAS hold time after W low Data setup time before CAS low or W low Data hold time after CAS low or W low Write pulse width ns ns ns ns ns ns ns ns Unit Min Max Min Max ns ns ns ns 13 15 13 15 Note 22: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT. 23: tWCS, tCWD, tRWD and tAWD and, tCPWD are specified as reference points only. If tWCS tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance throughout the entire cycle. If tCWD tCWD(min), tRWD tRWD (min), tAWD tAWD(min) and tCPWD tCPWD(min) (for Fast Page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) is satisfied, the DQ (at access time and until CAS or OE goes back to VIH ) is indetermi- nate. ≥ ≥ ≥ ≥ ≥ 13 15 tOEH OE hold time after W low ns tCWL tRWL tWP tDS 8 0 10 0 8 10 tDH Write pulse width Data hold time after CAS low or W low CAS hold time after W low RAS hold time after W low 13 15 13 15 Data setup time before CAS low or W low ns ns ns ns ns M5M46X400B-5,5S M5M46X800B-5,5S M5M465160B-5,5S M5M46X400B-6,6S M5M46X800B-6,6S M5M465160B-6,6S M5M46X400B-5,5S M5M46X800B-5,5S M5M465160B-5,5S M5M46X400B-6,6S M5M46X800B-6,6S M5M465160B-6,6S |
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