www.ti.com

65.27

(2)

TIMING RESISTANCE

vs

SWITCHING FREQUENCY

0

100

0

200

400

600

800

1000

200

300

400

500

600

100

0

200

300

400

500

600

400

600

800

1000

700

200

800

FEED-FORWARD IMPEDANCE

vs

SWITCHING FREQUENCY

UVLO OPERATION

TPS40060

TPS40061

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

APPLICATION INFORMATION (continued)

The PWM ramp must be faster than the master clock frequency or the PWM is prevented from starting. The

where:

•

•

See the section on UVLO operation for further description.

voltages is shown in Figure 3.

For low input voltage and high duty cycle applications, the voltage feed-forward may limit the duty cycle

prematurely. This does not occur for most applications. The voltage control loop controls the duty cycle and

regulates the output voltages. For more information on large duty cycle operation, refer to Application Note

(SLUA310).

Figure 2.

Figure 3.

The TPS40060 and TPS40061 use both fixed and variable (user programmable) UVLO protection. The fixed

UVLO monitors the BP10 and BP5 bypass voltages. The UVLO circuit holds the soft-start low until the BP5 and

BP10 voltage rails have exceeded their thresholds and the input voltage has exceed the user programmable

undervoltage threshold.

The TPS40060 and TPS40061 use the feed-forward pin, KFF, as a user programmable low-line UVLO detection.

This variable low-line UVLO threshold compares the PWM ramp duration to the oscillator clock period. An

undervoltage condition existis if the device receives a clock pulse before the ramp has reached 90% of its full

amplitude. The ramp duration is a function of the ramp slope, which is directly related to the current into the KFF

pin. The KFF current is a function of the input voltage and the resistance from KFF to the input voltage. The KFF

resistor can be referenced to the oscillator frequency as descibed in Equation 3:

8