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M34570MD-XXXFP Datasheet(PDF) 8 Page - Mitsubishi Electric Semiconductor |
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M34570MD-XXXFP Datasheet(HTML) 8 Page - Mitsubishi Electric Semiconductor |
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8 / 68 page  8 MITSUBISHI MICROCOMPUTERS 4570 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Fig. 1 AMC instruction execution example Fig. 2 RAR instruction execution example Fig. 3 Registers A, B and register E FUNCTION BLOCK OPERATIONS CPU (1) Arithmetic logic unit (ALU) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4-bit data addition, comparison, AND operation, OR operation, and bit manipulation. (2) Register A and carry flag (CY) Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to “1” when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A0 is stored in carry flag CY with the RAR instruction (Figure 2). Carry flag CY can be set to “1” with the SC instruction and cleared to “0” with the RC instruction. (3) Registers B and E Register B is a 4-bit register used for temporary storage of 4- bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3). (4) Register D Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 4). (CY) (M(DP)) (A) Addition ALU <Carry> <Result> CY A3 A2 A1 A0 A0 CY A3 A2 A1 <Rotation> RAR instruction <Set> SC instruction <Clear> RC instruction A3 A2 A1 A0 B3 B2 B1 B0 E7 E6 E5 E4 E3 E2 E1 E0 A3 A2 A1 A0 B3 B2 B1 B0 TAB instruction TEAB instruction TABE instruction TBA instruction Register B Register A Register B Register A Register E Fig. 4 TABP p instruction execution example Specifying address TABP p instruction p6 p5 p4 p3 p2 p1 p0 PCH DR2 DR1 DR0 A3 A2 A1 A0 PCL Immediate field value p The contents of register D ROM 84 0 Middle-order 4 bits Low-order 4 bits Register A (4) Register B (4) The contents of register A High-order 2 bits Register B (4) Register W5 (2) |
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