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SSTVF16859 Datasheet(PDF) 4 Page - NXP Semiconductors |
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SSTVF16859 Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 15 page Philips Semiconductors Product data sheet SSTVF16859 13-bit 1:2 SSTL_2 registered buffer for DDR 2004 Jul 12 4 56-TERMINAL CONFIGURATION 14 13 12 11 10 1 2 3 4 5 6 7 8 9 29 30 31 32 33 42 41 40 39 38 37 36 35 34 Q7A Q6A Q5A Q4A Q3A Q2A Q1A Q13B VDDQ Q12B Q11B Q10B Q9B Q8B D10 D9 D8 D7 GND CK D6 D5 D4 VREF VDDI VDDQ SW01040 CK RESET TERMINAL DESCRIPTION TERMINAL NUMBER SYMBOL NAME AND FUNCTION 1, 2, 3, 4, 5, 6, 7, 50, 51, 52, 53, 54, 56 Q13A–Q1A Data output 10, 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 22 Q13B–Q1B Data output 9, 17, 23, 27, 34, 44, 49, 55 VDDQ Power supply voltage 26, 33, 45 VDDI Power supply voltage 37, 48 GND Ground 24, 25, 28, 29, 30, 31, 39, 40, 41, 42, 43, 46, 47 D1–D13 Data input: clocked in on the crossing of the rising edge of CK and the falling edge of CK 32 VREF Input reference voltage 35, 36 CK, CK Positive and negative master clock input 51 RESET Asynchronous reset input: resets registers and disables data and clock differential input receivers |
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