M58LR128FT85ZB6E datasheet(11/82 Pages) STMICROELECTRONICS

Part #	M58LR128FT85ZB6E

Description	128 Mbit (8Mb x16, Multiple Bank, Multi-Level, Burst) 1.8V Supply Flash Memory

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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M58LR128FT, M58LR128FB

should be as close as possible to the pack-

age). See Figure 9., AC Measurement Load Cir-

cuit. The PCB trace widths should be sufficient

to carry the required VPP program and erase

currents.

BUS OPERATIONS

There are six standard bus operations that control

the device. These are Bus Read, Bus Write, Ad-

dress Latch, Output Disable, Standby and Reset.

See Table 3., Bus Operations, for a summary.

Typically glitches of less than 5ns on Chip Enable

or Write Enable are ignored by the memory and do

not affect Bus Write operations.

Bus Read. Bus Read operations are used to out-

put the contents of the Memory Array, the Elec-

tronic Signature, the Status Register and the

Common Flash Interface. Both Chip Enable and

Output Enable must be at VIL in order to perform a

read operation. The Chip Enable input should be

used to enable the device. Output Enable should

be used to gate data onto the output. The data

read depends on the previous command written to

the memory (see Command Interface section).

See Figures 10, 11, 12 and 13 Read AC Wave-

forms, and Tables 21 and 22 Read AC Character-

istics, for details of when the output becomes

valid.

Bus Write. Bus Write operations write Com-

mands to the memory or latch Input Data to be

programmed. A bus write operation is initiated

when Chip Enable and Write Enable are at VIL with

Output Enable at VIH. Commands, Input Data and

Addresses are latched on the rising edge of Write

Enable or Chip Enable, whichever occurs first. The

addresses can also be latched prior to the write

operation by toggling Latch Enable. In this case

the Latch Enable should be tied to VIH during the

bus write operation.

See Figures 16 and 17, Write AC Waveforms, and

Tables 23 and 24, Write AC Characteristics, for

details of the timing requirements.

Address Latch. Address latch operations input

valid addresses. Both Chip enable and Latch En-

able must be at VIL during address latch opera-

tions. The addresses are latched on the rising

edge of Latch Enable.

Output Disable. The outputs are high imped-

ance when the Output Enable is at VIH.

Standby. Standby disables most of the internal

circuitry allowing a substantial reduction of the cur-

rent consumption. The memory is in standby when

Chip Enable and Reset are at VIH. The power con-

sumption is reduced to the standby level IDD4 and

the outputs are set to high impedance, indepen-

dently from the Output Enable or Write Enable in-

puts. If Chip Enable switches to VIH during a

program or erase operation, the device enters

Standby mode when finished.

Reset. During Reset mode the memory is dese-

lected and the outputs are high impedance. The

memory is in Reset mode when Reset is at VIL.

The power consumption is reduced to the Standby

level, independently from the Chip Enable, Output

Enable or Write Enable inputs. If Reset is pulled to

VSS during a Program or Erase, this operation is

aborted and the memory content is no longer valid.

Table 3. Bus Operations

Note: 1. X = Don't care.

2. L can be tied to VIH if the valid address has been previously latched.

3. Depends on G.

4. WAIT signal polarity is configured using the Set Configuration Register command.

Operation

E

G

W

L

RP

WAIT(4)

DQ15-DQ0

Bus Read

VIL

VIH

VIL

(2)

VIH

Data Output

Bus Write

VIL

VIH

VIL

(2)

VIH

Data Input

Address Latch

VIL

X

VIH

VIL

VIH

Data Output or Hi-Z (3)

Output Disable

VIL

VIH

X

VIH

Hi-Z

Standby

VIH

XX

X

VIH

Hi-Z

Reset

X

VIL

Hi-Z

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