M24256-BW4BN6T datasheet(8/19 Pages) STMICROELECTRONICS

Part #	M24256-BW4BN6T

Description	256/128 Kbit Serial IC Bus EEPROM With Three Chip Enable Lines

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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M24256-B, M24128-B

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Acknowledge in Read Mode

In all read modes, the memory waits, after each

byte read, for an acknowledgment during the 9

th

bit time. If the master does not pull the SDA line

low during this time, the memory terminates the

data transfer and switches to its stand-by state.

internal address counter. The counter is then in-

cremented. The master terminates the transfer

with a STOP condition, as shown in Figure 8,

with-

out acknowledging the byte output.

Sequential Read

This mode can be initiated with either a Current

Address Read or a Random Address Read. The

master

does acknowledge the data byte output in

this case, and the memory continues to output the

next byte in sequence. To terminate the stream of

bytes, the master must

not acknowledge the last

byte output, and

must generate a STOP condition.

The output data comes from consecutive address-

es, with the internal address counter automatically

incremented after each byte output. After the last

memory address, the address counter ‘rolls-over’

and the memory continues to output data from

memory address 00h.

Figure 7. Write Cycle Polling Flowchart using ACK

WRITE Cycle

in Progress

AI01847

Addressing the

Memory

START Condition

DEVICE SELECT

with RW = 0

ACK

Returned

YES

NO

YES

NO

ReSTART

STOP

Proceed

WRITE Operation

Proceed

Random Address

READ Operation

Send

Byte Address

First byte of instruction

with RW = 0 already

decoded by M24xxx

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M24256-BW4BN6T Datasheet(PDF) 8 Page - STMicroelectronics

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