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PRELIMINARY DATA

February 2000

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M24256-B

M24128-B

256/128 Kbit Serial I C Bus EEPROM

With Three Chip Enable Lines

s

s

Supports 400 kHz Protocol

s

Single Supply Voltage:

– 4.5V to 5.5V for M24xxx-B

– 2.5V to 5.5V for M24xxx-BW

– 1.8V to 3.6V for M24xxx-BR

s

Hardware Write Control

s

BYTE and PAGE WRITE (up to 64 Bytes)

s

RANDOM and SEQUENTIAL READ Modes

s

Self-Timed Programming Cycle

s

Automatic Address Incrementing

s

Enhanced ESD/Latch-Up Behavior

s

100000 Erase/Write Cycles (minimum)

s

40 Year Data Retention (minimum)

DESCRIPTION

grammable memory (EEPROM) devices are orga-

nized as 32Kx8 bits (M24256-B) and 16Kx8 bits

(M24128-B).

These memory devices are compatible with the

serial interface that uses a bi-directional data bus

and serial clock. The memory carries a built-in 4-

bit unique Device Type Identifier code (1010) in

Figure 1. Logic Diagram

AI02809

SDA

VCC

M24256-B

M24128-B

WC

SCL

VSS

3

E0-E2

Table 1. Signal Names

E0, E1, E2

Chip Enable Inputs

SDA

Serial Data/Address Input/

Output

SCL

Serial Clock

WC

Write Control

VCC

Supply Voltage

VSS

Ground

PSDIP8 (BN)

0.25 mm frame

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

8

1

8

1

8

1

TSSOP14 (DL)

169 mil width

14

1