COMMERCIALTEMPERATURERANGE

IDTCV119E

CLOCKGENERATORFORDESKTOPPCPLATFORMS

11

BYTE 26: CPU PLL CONTROL

Bit

Output(s)Affected

Description/Function

0

1

Type

Power On

7

WDBS2

At the event of WD hard alarm time out,

RW

1

6

WDBS1

If Byte 32 bit 7 = 1, CPU frequency is

RW

0

5

WDBS0

RW

0

4

CSMC2

CPU SMC2, SMC table

RW

0

3

CSMC1

CPU SMC1, SMC table

RW

1

2

CSMC0

CPU SMC0, SMC table

RW

0

1

CPN9

CPU PLL N9

RW

0

0

CPN8

CPU PLL N8

RW

1

NOTE:

1. See SW FREQUENCY SELECTION table.

BYTE 27: CPU PLL N PROGRAMMING

In CPU N programming mode, CPU frequency = CPN[9:0] * band resolution. CPN0 has to be written for the CPN[9:0] to be loaded into PLL N divider. See

SWFREQUENCYSELECTIONtable.

Bit

Output(s)Affected

Description/Function

0

1

Type

Power On

7

CPN7

CPU PLL N7

RW

0

6

CPN6

CPU PLL N6

RW

0

5

CPN5

CPU PLL N5

RW

1

4

CPN4

CPU PLL N4

RW

0

3

CPN3

CPU PLL N3

RW

1

2

CPN2

CPU PLL N2

RW

0

1

CPN1

CPU PLL N1

RW

1

0

CPN0

CPU PLL N0

RW

0

BYTE 28: AGP/PCI PLL CONTROL

Bit

Output(s)Affected

Description/Function

0

1

Type

Power On

7

AFS2

See AGP/PCI FREQUENCY SELECTION table

RW

0

6

AFS1

See AGP/PCI FREQUENCY SELECTION table

RW

0

5

AFS0

See AGP/PCI FREQUENCY SELECTION table

RW

0

4

WDAFS2

AGP/PCI WD hard alarm time out frequency selection

RW

0

3

WDAFS1

AGP/PCI WD hard alarm time out frequency selection

RW

0

2

WDAFSO

AGP/PCI WD hard alarm time out frequency selection

RW

0

1

APN9

AGP/PCI PLL N9

RW

0

0

APN8

AGP/PCI PLL N8

RW

1