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M28W320CT100ZB6T Datasheet(PDF) 10 Page - STMicroelectronics |
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M28W320CT100ZB6T Datasheet(HTML) 10 Page - STMicroelectronics |
10 / 42 page M28W320CT, M28W320CB 10/42 Status Register bit b7 returns ’0’ while the erasure is in progress and ’1’ when it has completed. After completion the Status Register bit b5 returns ’1’ if there has been an Erase Failure. Status register bit b1 returns ’1’ if the user is attempting to pro- gram a protected block. Status Register bit b3 re- turns a ’1’ if VPP is below VPPLK. Erase aborts if RP turns to VIL. As data integrity cannot be guaranteed when the erase operation is aborted, the erase must be repeated. A Clear Sta- tus Register instruction must be issued to reset b1, b3, b4 and b5 of the Status Register. During the execution of the erase by the P/E.C., the memory accepts only the RSR (Read Status Register) and PES (Program/Erase Suspend) instructions. Table 10. Instructions Note: 1. X = Don’t Care. 2. The first cycle of the RD, RSR, RSIG or RCFI instruction is followed by read operations in the memory array or special register. Any number of read cycle can occur after one command cycle. 3. The signature address recognized are listed in the Tables 6, 7 and 8. 4. Address 1 and Address 2 must be consecutive address differing only for address bit A0. 5. A read cycle after a CLSR instruction wil l output the memory array. Mne- mon ic Instruction Cycles 1st Cycle 2nd Cycle 3nd Cycle Operat. Addr. (1) Data Operat. Addr. Data Operat. Addr. Data RD Read Memory Array 1+ Write X FFh Read (2) Read Address Data RSR Read Status Register 1+ Write X 70h Read (2) X Status Register RSIG Read Electronic Signature 1+ Write X 90h or 98h Read (2) Signature Address (3) Data RCFI Read CFI 1+ Write 55h 98h or 90h Read (2) CFI Address Query EE Erase 2 Write X 20h Write Block Address D0h PG Program 2 Write X 40h or 10h Write Address Data Input DPG (4) Double Word Program 3 Write X 30h Write Address 1 Data Input Write Address 2 Data Input CLRS (5) Clear Status Register 1 Write X 50h PES Program/ Erase Suspend 1 Write X B0h PER Program/ Erase Resume 1 Write X D0h BP Block Protect 2 Write X 60h Write Block Address 01h BU Block Unprotect 2 Write X 60h Write Block Address D0h BL Block Lock 2 Write X 60h Write Block Address 2Fh PRP Protection Register Program 2 Write X C0h Write Address Data Input Erase (EE) Block erasure sets all the bits within the selected block to ’1’. One block at a time can be erased. It is not necessary to program the block with 00h as the P/E.C. will do it automatically before erasing. This instruction uses two write cycles. The first command written is the Erase Set up command 20h. The second command is the Erase Confirm command D0h. An address within the block to be erased is given and latched into the memory dur- ing the input of the second command. If the sec- ond command given is not an erase confirm, the status register bits b4 and b5 are set and the in- struction aborts. Read operations output the status register after erasure has started. |
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